fill empty module body with "begin end" (#305)

* fill empty module body with "begin end"

apparently vivado treats an empty module as a black box and triggers an error

* Changed empty module to use always @(*) begin end

1 files changed, 1 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 26b1f3d9..92cb7a54 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -612,6 +612,7 @@ class VerilogEmitter extends Emitter {
         }
         emit(Seq(");"))
 
+        if (declares.isEmpty && assigns.isEmpty) emit(Seq(tab, "always @(*) begin end"))
         for (x <- declares) emit(Seq(tab, x))
         for (x <- instdeclares) emit(Seq(tab, x))
         for (x <- assigns) emit(Seq(tab, x))