use BoolType for UIntType(IntWidth(1))

5 files changed, 8 insertions, 8 deletions

diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index deea3c0e..4cc0bdb9 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -80,9 +80,9 @@ object ExpandWhens extends Pass {
   }
 
   private def AND(e1: Expression, e2: Expression) =
-    DoPrim(And, Seq(e1, e2), Nil, UIntType(IntWidth(1)))
+    DoPrim(And, Seq(e1, e2), Nil, BoolType)
   private def NOT(e: Expression) =
-    DoPrim(Eq, Seq(e, zero), Nil, UIntType(IntWidth(1)))
+    DoPrim(Eq, Seq(e, zero), Nil, BoolType)
 
   // ------------ Pass -------------------
   def run(c: Circuit): Circuit = {
diff --git a/src/main/scala/firrtl/passes/MemUtils.scala b/src/main/scala/firrtl/passes/MemUtils.scala
index 21884661..505ad0da 100644
--- a/src/main/scala/firrtl/passes/MemUtils.scala
+++ b/src/main/scala/firrtl/passes/MemUtils.scala
@@ -193,7 +193,7 @@ object MemPortUtils {
 
   def rwPortToFlattenBundle(mem: DefMemory) = BundleType(
     defaultPortSeq(mem) ++ Seq(
-      Field("wmode", Default, UIntType(IntWidth(1))),
+      Field("wmode", Default, BoolType),
       Field("wdata", Default, flattenType(mem.dataType)),
       Field("rdata", Flip, flattenType(mem.dataType))
     ) ++ (if (!containsInfo(mem.info, "maskGran")) Nil
@@ -220,7 +220,7 @@ object MemPortUtils {
       Field("mask", Default, createMask(mem.dataType))))
     val rwType = BundleType(defaultPortSeq(mem) ++ Seq(
       Field("rdata", Flip, mem.dataType),
-      Field("wmode", Default, UIntType(IntWidth(1))),
+      Field("wmode", Default, BoolType),
       Field("wdata", Default, mem.dataType),
       Field("wmask", Default, createMask(mem.dataType))))
     BundleType(
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 9057c60d..7f53fac8 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -200,9 +200,9 @@ object Legalize extends Pass {
     lazy val msb = width - 1
     if (amount >= width) {
       e.tpe match {
-        case UIntType(_) => UIntLiteral(0, IntWidth(1))
+        case UIntType(_) => zero
         case SIntType(_) =>
-          val bits = DoPrim(Bits, e.args, Seq(msb, msb), UIntType(IntWidth(1)))
+          val bits = DoPrim(Bits, e.args, Seq(msb, msb), BoolType)
           DoPrim(AsSInt, Seq(bits), Seq.empty, SIntType(IntWidth(1)))
         case t => error(s"Unsupported type ${t} for Primop Shift Right")
       }
diff --git a/src/main/scala/firrtl/passes/RemoveAccesses.scala b/src/main/scala/firrtl/passes/RemoveAccesses.scala
index 08f08eac..933c3543 100644
--- a/src/main/scala/firrtl/passes/RemoveAccesses.scala
+++ b/src/main/scala/firrtl/passes/RemoveAccesses.scala
@@ -15,7 +15,7 @@ object RemoveAccesses extends Pass {
   def name = "Remove Accesses"
 
   private def AND(e1: Expression, e2: Expression) =
-    DoPrim(And, Seq(e1, e2), Nil, UIntType(IntWidth(1)))
+    DoPrim(And, Seq(e1, e2), Nil, BoolType)
 
   private def EQV(e1: Expression, e2: Expression): Expression =
     DoPrim(Eq, Seq(e1, e2), Nil, e1.tpe)
diff --git a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
index ca860ab6..b71c0dc3 100644
--- a/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
+++ b/src/main/scala/firrtl/passes/RemoveCHIRRTL.scala
@@ -174,7 +174,7 @@ object RemoveCHIRRTL extends Pass {
         case Some(p) => g match {
           case FEMALE =>
             has_write_mport = true
-            if (p.rdwrite) has_readwrite_mport = Some(SubField(p.exp, "wmode", UIntType(IntWidth(1))))
+            if (p.rdwrite) has_readwrite_mport = Some(SubField(p.exp, "wmode", BoolType))
             SubField(p.exp, p.female, tpe)
           case MALE =>
             SubField(p.exp, p.male, tpe)