diff options
| author | Donggyu Kim | 2016-09-08 22:17:02 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-09-13 17:31:14 -0700 |
| commit | 1f90624762c419ab8e2ac51f9ddbca58fff07815 (patch) | |
| tree | 20a892b73ba144dd0583678d096e8f6dcd34a233 /src | |
| parent | b6a12c77223f50be57a682fb4be198ed8ffc3511 (diff) | |
remove VIndent
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Emitter.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala index 85955088..26b1f3d9 100644 --- a/src/main/scala/firrtl/Emitter.scala +++ b/src/main/scala/firrtl/Emitter.scala @@ -53,7 +53,6 @@ object FIRRTLEmitter extends Emitter { def run(c: Circuit, w: Writer) = w.write(c.serialize) } -case class VIndent() case class VRandom(width: BigInt) extends Expression { def tpe = UIntType(IntWidth(width)) def nWords = (width + 31) / 32 @@ -127,7 +126,6 @@ class VerilogEmitter extends Emitter { case (i: Int) => w write i.toString case (i: Long) => w write i.toString case (i: BigInt) => w write i.toString - case (t: VIndent) => w write " " case (s: Seq[Any]) => s foreach (emit(_, top + 1)) if (top == 0) w write "\n" |