From 1f90624762c419ab8e2ac51f9ddbca58fff07815 Mon Sep 17 00:00:00 2001
From: Donggyu Kim
Date: Thu, 8 Sep 2016 22:17:02 -0700
Subject: remove VIndent

---
 src/main/scala/firrtl/Emitter.scala | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 85955088..26b1f3d9 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -53,7 +53,6 @@ object FIRRTLEmitter extends Emitter {
   def run(c: Circuit, w: Writer) = w.write(c.serialize)
 }
 
-case class VIndent()
 case class VRandom(width: BigInt) extends Expression {
   def tpe = UIntType(IntWidth(width))
   def nWords = (width + 31) / 32
@@ -127,7 +126,6 @@ class VerilogEmitter extends Emitter {
       case (i: Int) => w write i.toString
       case (i: Long) => w write i.toString
       case (i: BigInt) => w write i.toString
-      case (t: VIndent) => w write "   "
       case (s: Seq[Any]) =>
         s foreach (emit(_, top + 1))
         if (top == 0) w write "\n"
-- 
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