Use parens on Unit methods

4 files changed, 7 insertions, 7 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index f96c0419..435bc484 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -426,7 +426,7 @@ class VerilogEmitter extends Emitter {
         }
       }
 
-      def build_ports: Unit = m.ports.zipWithIndex foreach {case (p, i) =>
+      def build_ports(): Unit = m.ports.zipWithIndex foreach {case (p, i) =>
         p.direction match {
           case Input =>
             portdefs += Seq(p.direction, "  ", p.tpe, " ", p.name)
@@ -602,7 +602,7 @@ class VerilogEmitter extends Emitter {
         case s => s
       }
    
-      def emit_streams {
+      def emit_streams() {
         emit(Seq("module ", m.name, "("))
         for ((x, i) <- portdefs.zipWithIndex) {
           if (i != portdefs.size - 1)
diff --git a/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala b/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
index 4f55722b..d229aaf3 100644
--- a/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
+++ b/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
@@ -231,10 +231,10 @@ class YamlFileWriter(file: String) {
   def append(in: YamlValue) {
     outputBuffer append s"$separator${in.prettyPrint}"
   }
-  def dump {
+  def dump() {
     val outputFile = new PrintWriter(file)
     outputFile write outputBuffer.toString
-    outputFile.close
+    outputFile.close()
   }
 }
 
@@ -247,7 +247,7 @@ class AnnotateValidMemConfigs(reader: Option[YamlFileReader]) extends Pass {
   case class SRAMCompilerSet(
       sp: Option[SRAMCompiler] = None, 
       dp: Option[SRAMCompiler] = None) {
-    def serialize = {
+    def serialize() = {
       sp match {
         case None =>
         case Some(p) => p.serialize
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 8264c6ac..7b37cf65 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -46,7 +46,7 @@ class PassExceptions(exceptions: Seq[PassException]) extends Exception("\n" + ex
 class Errors {
   val errors = collection.mutable.ArrayBuffer[PassException]()
   def append(pe: PassException) = errors.append(pe)
-  def trigger = errors.size match {
+  def trigger() = errors.size match {
     case 0 =>
     case 1 => throw errors.head
     case _ =>
diff --git a/src/main/scala/firrtl/passes/ReplSeqMem.scala b/src/main/scala/firrtl/passes/ReplSeqMem.scala
index 87b9df11..0933eefe 100644
--- a/src/main/scala/firrtl/passes/ReplSeqMem.scala
+++ b/src/main/scala/firrtl/passes/ReplSeqMem.scala
@@ -52,7 +52,7 @@ class ConfWriter(filename: String) {
     val conf = s"name ${m.name} depth ${m.depth} width ${width} ports ${ports} ${maskGranConf} \n"
     outputBuffer.append(conf)
   }
-  def serialize = {
+  def serialize() = {
     val outputFile = new PrintWriter(filename)
     outputFile.write(outputBuffer.toString)
     outputFile.close()