use .isEmpty, .nonEmpty, isDefined

5 files changed, 10 insertions, 10 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 902dfecd..f96c0419 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -616,7 +616,7 @@ class VerilogEmitter extends Emitter {
         for (x <- declares) emit(Seq(tab, x))
         for (x <- instdeclares) emit(Seq(tab, x))
         for (x <- assigns) emit(Seq(tab, x))
-        if (!initials.isEmpty) {
+        if (initials.nonEmpty) {
           emit(Seq("`ifdef RANDOMIZE"))
           emit(Seq("  integer initvar;"))
           emit(Seq("  initial begin"))
@@ -631,7 +631,7 @@ class VerilogEmitter extends Emitter {
           emit(Seq("`endif"))
         }
  
-        for (clk_stream <- at_clock if !clk_stream._2.isEmpty) {
+        for (clk_stream <- at_clock if clk_stream._2.nonEmpty) {
           emit(Seq(tab, "always @(posedge ", clk_stream._1, ") begin"))
           for (x <- clk_stream._2) emit(Seq(tab, tab, x))
           emit(Seq(tab, "end"))
diff --git a/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala b/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
index f80d4a0c..4f55722b 100644
--- a/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
+++ b/src/main/scala/firrtl/passes/AnnotateValidMemConfigs.scala
@@ -39,7 +39,7 @@ case class MemDimension(
     rules: Option[DimensionRules],
     set: Option[List[Int]]) {
   require (
-    if (rules == None) set != None else set == None, 
+    if (rules.isEmpty) set.isDefined else set.isEmpty,
     "Should specify either rules or a list of valid options, but not both"
   )
   def getValid = set.getOrElse(rules.get.getValid).sorted
@@ -120,7 +120,7 @@ case class SRAMCompiler(
     fillWMask: Boolean) {
   require(portType == "RW" || portType == "R,W", "Memory must be single port RW or dual port R,W")
   require(
-    (configFile != None && configPattern != None && wMaskArg != None) || configFile == None, 
+    (configFile.isDefined && configPattern.isDefined && wMaskArg.isDefined) || configFile.isEmpty,
     "Config pattern must be provided with config file"
   ) 
   def ymuxVals = rules.map(_.ymux._1).sortWith(_ < _)
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index 12dfb497..23d8caf1 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -72,11 +72,11 @@ class InlineInstances (transID: TransID) extends Transform {
       }
 
       moduleNames.foreach{mn => checkExists(mn.name)}
-      if (!errors.isEmpty) throw new PassExceptions(errors)
+      if (errors.nonEmpty) throw new PassExceptions(errors)
       moduleNames.foreach{mn => checkExternal(mn.name)}
-      if (!errors.isEmpty) throw new PassExceptions(errors)
+      if (errors.nonEmpty) throw new PassExceptions(errors)
       instanceNames.foreach{cn => checkInstance(cn)}
-      if (!errors.isEmpty) throw new PassExceptions(errors)
+      if (errors.nonEmpty) throw new PassExceptions(errors)
    }
 
    def run(c: Circuit, modsToInline: Set[ModuleName], instsToInline: Set[ComponentName]): TransformResult = {
diff --git a/src/main/scala/firrtl/passes/ReplSeqMem.scala b/src/main/scala/firrtl/passes/ReplSeqMem.scala
index c2c1b303..87b9df11 100644
--- a/src/main/scala/firrtl/passes/ReplSeqMem.scala
+++ b/src/main/scala/firrtl/passes/ReplSeqMem.scala
@@ -44,8 +44,8 @@ class ConfWriter(filename: String) {
     // legacy
     val maskGran = getInfo(m.info, "maskGran")
     val readers = List.fill(m.readers.length)("read")
-    val writers = List.fill(m.writers.length)(if (maskGran == None) "write" else "mwrite")
-    val readwriters = List.fill(m.readwriters.length)(if (maskGran == None) "rw" else "mrw")
+    val writers = List.fill(m.writers.length)(if (maskGran.isEmpty) "write" else "mwrite")
+    val readwriters = List.fill(m.readwriters.length)(if (maskGran.isEmpty) "rw" else "mrw")
     val ports = (writers ++ readers ++ readwriters) mkString ","
     val maskGranConf = maskGran match { case None => "" case Some(p) => s"mask_gran $p" }
     val width = bitWidth(m.dataType)
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index 758791b2..a5eee002 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -148,7 +148,7 @@ object Uniquify extends Pass {
       case (from: BundleType, to: BundleType) =>
         (from.fields zip to.fields flatMap { case (f, t) =>
           val eltsMap = createNameMapping(f.tpe, t.tpe)
-          if ((f.name != t.name) || (eltsMap.size > 0)) {
+          if ((f.name != t.name) || eltsMap.nonEmpty) {
             Map(f.name -> NameMapNode(t.name, eltsMap))
           } else {
             Map[String, NameMapNode]()