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chisel3/ModuleVec.fir doesn't work because incorrecly generated?
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Conflicts:
TODO
src/main/stanza/passes.stanza
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not propogating to the input widths, for primops
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and alternate were always assumed different, causing a huge blow-up in logic
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correctly handle it in compiler.
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missing primops
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referenced, has an inferred kind
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generate flo
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instructions and renamed concat -> cat, equal -> eq, and added neq and neg
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lowering. Finished expand-whens. Needs more thorough testing of instances
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WRegInit and removing Null and initialize-register pass
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all pass. Minimal removal of letrec to get WritePort to work correctly - a more thorough removeal is still needed
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call firrtl correctly to enable/disable them
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justification. Added response to feedback, locatd in notes/feedbackQA*. Use two different mains, one for testing and one for deployment (make build vs make build-deploy).
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allows the compiler to print after each pass to ease debugging
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with a new IR construct - Null. LetRec is not implemented, but is
marked with a TODO.
Test cases for this pass are now located in
test/passes/initialize-register
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