Fixed bug in primop lowering during type inference. Added reduce instructions and renamed concat -> cat, equal -> eq, and added neq and neg

10 files changed, 56 insertions, 43 deletions

diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index f3754a32..e00dd9c2 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -16,10 +16,10 @@ circuit top :
       ; CHECK: wire b$x : UInt(32)
       ; CHECK: wire b$y : UInt(32)
       ; CHECK: b$x := a$0$x
-      ; CHECK: when equal-uu(i, UInt(1)) :
+      ; CHECK: when eq-uu(i, UInt(1)) :
       ; CHECK:    b$x := a$1$x
       ; CHECK: a$0$y := b$y
-      ; CHECK: when equal-uu(i, UInt(1)) :
+      ; CHECK: when eq-uu(i, UInt(1)) :
       ; CHECK:    a$1$y := b$y
       j := b
       
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index ea134c2f..aa43644c 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -7,7 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-wrap(x, y)
-      ;CHECK: z@<t:UInt> := sub-wrap(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
+      ;CHECK: z@<t:UInt> := sub-wrap-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
    module gcd :
       input a : UInt(16)
       input b : UInt(16)
@@ -20,7 +20,7 @@ circuit top :
       x.init := UInt(0)
       y.init := UInt(42)
       when gt(x, y) :
-      ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
+      ;CHECK: when gt-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
          ;CHECK: inst s of subtracter@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt(1)@<t:UInt>}>
          s.x := x
@@ -38,8 +38,8 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal(v, UInt(0))
-      ;CHECK: v@<t:UInt> := equal(v@<t:UInt>, UInt(0))@<t:UInt>
+      v := eq(v, UInt(0))
+      ;CHECK: v@<t:UInt> := eq-uu(v@<t:UInt>, UInt(0))@<t:UInt>
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index 7e7342ae..2c37f361 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -9,120 +9,133 @@ circuit top :
       wire d : SInt(8)
       wire e : UInt(1)
 
-      node vadd = add(a, c)    ;CHECK: node vadd = add(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vadd = add(a, c)    ;CHECK: node vadd = add-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wadd-uu = add-uu(a, b) ;CHECK: node wadd-uu = add-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xadd-us = add-us(a, d) ;CHECK: node xadd-us = add-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node yadd-su = add-su(c, b) ;CHECK: node yadd-su = add-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zadd-ss = add-ss(c, d) ;CHECK: node zadd-ss = add-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vsub = sub(a, c)    ;CHECK: node vsub = sub(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vsub = sub(a, c)    ;CHECK: node vsub = sub-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wsub-uu = sub-uu(a, b) ;CHECK: node wsub-uu = sub-uu(a@<t:UInt>, b@<t:UInt>)@<t:SInt>
       node xsub-us = sub-us(a, d) ;CHECK: node xsub-us = sub-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node ysub-su = sub-su(c, b) ;CHECK: node ysub-su = sub-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zsub-ss = sub-ss(c, d) ;CHECK: node zsub-ss = sub-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vmul = mul(a, c)    ;CHECK: node vmul = mul(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vmul = mul(a, c)    ;CHECK: node vmul = mul-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wmul-uu = mul-uu(a, b) ;CHECK: node wmul-uu = mul-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xmul-us = mul-us(a, d) ;CHECK: node xmul-us = mul-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node ymul-su = mul-su(c, b) ;CHECK: node ymul-su = mul-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zmul-ss = mul-ss(c, d) ;CHECK: node zmul-ss = mul-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vdiv = div(a, c)    ;CHECK: node vdiv = div(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vdiv = div(a, c)    ;CHECK: node vdiv = div-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wdiv-uu = div-uu(a, b) ;CHECK: node wdiv-uu = div-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xdiv-us = div-us(a, d) ;CHECK: node xdiv-us = div-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node ydiv-su = div-su(c, b) ;CHECK: node ydiv-su = div-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zdiv-ss = div-ss(c, d) ;CHECK: node zdiv-ss = div-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vmod = mod(a, c)    ;CHECK: node vmod = mod(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+      node vmod = mod(a, c)    ;CHECK: node vmod = mod-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wmod-uu = mod-uu(a, b) ;CHECK: node wmod-uu = mod-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xmod-us = mod-us(a, d) ;CHECK: node xmod-us = mod-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
       node ymod-su = mod-su(c, b) ;CHECK: node ymod-su = mod-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zmod-ss = mod-ss(c, d) ;CHECK: node zmod-ss = mod-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vquo = quo(a, c)    ;CHECK: node vquo = quo(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vquo = quo(a, c)    ;CHECK: node vquo = quo-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wquo-uu = quo-uu(a, b) ;CHECK: node wquo-uu = quo-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xquo-us = quo-us(a, d) ;CHECK: node xquo-us = quo-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node yquo-su = quo-su(c, b) ;CHECK: node yquo-su = quo-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zquo-ss = quo-ss(c, d) ;CHECK: node zquo-ss = quo-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vrem = rem(a, c)    ;CHECK: node vrem = rem(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vrem = rem(a, c)    ;CHECK: node vrem = rem-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wrem-uu = rem-uu(a, b) ;CHECK: node wrem-uu = rem-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xrem-us = rem-us(a, d) ;CHECK: node xrem-us = rem-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node yrem-su = rem-su(c, b) ;CHECK: node yrem-su = rem-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zrem-ss = rem-ss(c, d) ;CHECK: node zrem-ss = rem-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vadd-wrap = add-wrap(a, c)    ;CHECK: node vadd-wrap = add-wrap(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vadd-wrap = add-wrap(a, c)    ;CHECK: node vadd-wrap = add-wrap-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wadd-wrap-uu = add-wrap-uu(a, b) ;CHECK: node wadd-wrap-uu = add-wrap-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xadd-wrap-us = add-wrap-us(a, d) ;CHECK: node xadd-wrap-us = add-wrap-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node yadd-wrap-su = add-wrap-su(c, b) ;CHECK: node yadd-wrap-su = add-wrap-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zadd-wrap-ss = add-wrap-ss(c, d) ;CHECK: node zadd-wrap-ss = add-wrap-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vsub-wrap = sub-wrap(a, c)    ;CHECK: node vsub-wrap = sub-wrap(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vsub-wrap = sub-wrap(a, c)    ;CHECK: node vsub-wrap = sub-wrap-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wsub-wrap-uu = sub-wrap-uu(a, b) ;CHECK: node wsub-wrap-uu = sub-wrap-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xsub-wrap-us = sub-wrap-us(a, d) ;CHECK: node xsub-wrap-us = sub-wrap-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node ysub-wrap-su = sub-wrap-su(c, b) ;CHECK: node ysub-wrap-su = sub-wrap-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zsub-wrap-ss = sub-wrap-ss(c, d) ;CHECK: node zsub-wrap-ss = sub-wrap-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vlt = lt(a, c)    ;CHECK: node vlt = lt(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+      node vlt = lt(a, c)    ;CHECK: node vlt = lt-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wlt-uu = lt-uu(a, b) ;CHECK: node wlt-uu = lt-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xlt-us = lt-us(a, d) ;CHECK: node xlt-us = lt-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
       node ylt-su = lt-su(c, b) ;CHECK: node ylt-su = lt-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zlt-ss = lt-ss(c, d) ;CHECK: node zlt-ss = lt-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vleq = leq(a, c)    ;CHECK: node vleq = leq(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+      node vleq = leq(a, c)    ;CHECK: node vleq = leq-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wleq-uu = leq-uu(a, b) ;CHECK: node wleq-uu = leq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xleq-us = leq-us(a, d) ;CHECK: node xleq-us = leq-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
       node yleq-su = leq-su(c, b) ;CHECK: node yleq-su = leq-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zleq-ss = leq-ss(c, d) ;CHECK: node zleq-ss = leq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vgt = gt(a, c)    ;CHECK: node vgt = gt(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+      node vgt = gt(a, c)    ;CHECK: node vgt = gt-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wgt-uu = gt-uu(a, b) ;CHECK: node wgt-uu = gt-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xgt-us = gt-us(a, d) ;CHECK: node xgt-us = gt-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
       node ygt-su = gt-su(c, b) ;CHECK: node ygt-su = gt-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zgt-ss = gt-ss(c, d) ;CHECK: node zgt-ss = gt-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vgeq = geq(a, c)    ;CHECK: node vgeq = geq(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+      node vgeq = geq(a, c)    ;CHECK: node vgeq = geq-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wgeq-uu = geq-uu(a, b) ;CHECK: node wgeq-uu = geq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xgeq-us = geq-us(a, d) ;CHECK: node xgeq-us = geq-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
       node ygeq-su = geq-su(c, b) ;CHECK: node ygeq-su = geq-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zgeq-ss = geq-ss(c, d) ;CHECK: node zgeq-ss = geq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vequal = equal(a, b)    ;CHECK: node vequal = equal(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node wequal-uu = equal-uu(a, b) ;CHECK: node wequal-uu = equal-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node zequal-ss = equal-ss(c, d) ;CHECK: node zequal-ss = equal-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
+      node vneq = neq(a, b)    ;CHECK: node vneq = neq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node wneq-uu = neq-uu(a, b) ;CHECK: node wneq-uu = neq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node zneq-ss = neq-ss(c, d) ;CHECK: node zneq-ss = neq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vmux = mux(e, a, b)    ;CHECK: node vmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node veq = eq(a, b)    ;CHECK: node veq = eq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node weq-uu = eq-uu(a, b) ;CHECK: node weq-uu = eq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node zeq-ss = eq-ss(c, d) ;CHECK: node zeq-ss = eq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
+   
+      node vmux = mux(e, a, b)    ;CHECK: node vmux = mux-uu(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node wmux-uu = mux-uu(e, a, b) ;CHECK: node wmux-uu = mux-uu(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node zmux-ss = mux-ss(e, c, d) ;CHECK: node zmux-ss = mux-ss(e@<t:UInt>, c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vpad = pad(a, 10)   ;CHECK: node vpad = pad(a@<t:UInt>, 10)@<t:UInt>
+      node vpad = pad(a, 10)   ;CHECK: node vpad = pad-u(a@<t:UInt>, 10)@<t:UInt>
       node wpad-u = pad-u(a, 10) ;CHECK: node wpad-u = pad-u(a@<t:UInt>, 10)@<t:UInt>
       node zpad-s = pad-s(c, 10) ;CHECK: node zpad-s = pad-s(c@<t:SInt>, 10)@<t:SInt>
    
-      node vas-UInt = as-UInt(d)   ;CHECK: node vas-UInt = as-UInt(d@<t:SInt>)@<t:UInt>
+      node vas-UInt = as-UInt(d)   ;CHECK: node vas-UInt = as-UInt-s(d@<t:SInt>)@<t:UInt>
       node was-UInt-u = as-UInt-u(a) ;CHECK: node was-UInt-u = as-UInt-u(a@<t:UInt>)@<t:UInt>
       node zas-UInt-s = as-UInt-s(c) ;CHECK: node zas-UInt-s = as-UInt-s(c@<t:SInt>)@<t:UInt>
    
-      node vas-SInt = as-SInt(a)   ;CHECK: node vas-SInt = as-SInt(a@<t:UInt>)@<t:SInt>
+      node vas-SInt = as-SInt(a)   ;CHECK: node vas-SInt = as-SInt-u(a@<t:UInt>)@<t:SInt>
       node was-SInt-u = as-SInt-u(a) ;CHECK: node was-SInt-u = as-SInt-u(a@<t:UInt>)@<t:SInt>
       node zas-SInt-s = as-SInt-s(c) ;CHECK: node zas-SInt-s = as-SInt-s(c@<t:SInt>)@<t:SInt>
    
-      node vshl = shl(a, 10)   ;CHECK: node vshl = shl(a@<t:UInt>, 10)@<t:UInt>
+      node vshl = shl(a, 10)   ;CHECK: node vshl = shl-u(a@<t:UInt>, 10)@<t:UInt>
       node wshl-u = shl-u(a, 10) ;CHECK: node wshl-u = shl-u(a@<t:UInt>, 10)@<t:UInt>
       node zshl-s = shl-s(c, 10) ;CHECK: node zshl-s = shl-s(c@<t:SInt>, 10)@<t:SInt>
    
-      node vshr = shr(a, 10)   ;CHECK: node vshr = shr(a@<t:UInt>, 10)@<t:UInt>
+      node vshr = shr(a, 10)   ;CHECK: node vshr = shr-u(a@<t:UInt>, 10)@<t:UInt>
       node wshr-u = shr-u(a, 10) ;CHECK: node wshr-u = shr-u(a@<t:UInt>, 10)@<t:UInt>
       node zshr-s = shr-s(c, 10) ;CHECK: node zshr-s = shr-s(c@<t:SInt>, 10)@<t:SInt>
    
-      node vconvert = convert(a)   ;CHECK: node vconvert = convert(a@<t:UInt>)@<t:SInt>
+      node vconvert = convert(a)   ;CHECK: node vconvert = convert-u(a@<t:UInt>)@<t:SInt>
       node wconvert-u = convert-u(a) ;CHECK: node wconvert-u = convert-u(a@<t:UInt>)@<t:SInt>
       node zconvert-s = convert-s(c) ;CHECK: node zconvert-s = convert-s(c@<t:SInt>)@<t:SInt>
    
+      node vneg = neg(a)   ;CHECK: node vneg = neg-u(a@<t:UInt>)@<t:UInt>
+      node wneg-u = neg-u(a) ;CHECK: node wneg-u = neg-u(a@<t:UInt>)@<t:UInt>
+      node zneg-s = neg-s(c) ;CHECK: node zneg-s = neg-s(c@<t:SInt>)@<t:UInt>
+   
       node uand = bit-and(a, b) ;CHECK: node uand = bit-and(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node vor = bit-or(a, b)  ;CHECK: node vor = bit-or(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node wxor = bit-xor(a, b) ;CHECK: node wxor = bit-xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node xconcat = concat(a, b) ;CHECK: node xconcat = concat(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node xcat = cat(a, b) ;CHECK: node xcat = cat(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node ybit = bit(a, 0) ;CHECK: node ybit = bit(a@<t:UInt>, 0)@<t:UInt>
       node zbits = bits(a, 2, 0) ;CHECK: node zbits = bits(a@<t:UInt>, 2, 0)@<t:UInt>
+
+      node uand-reduce = bit-and-reduce(a, b, a) ;CHECK: node uand-reduce = bit-and-reduce(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node uor-reduce = bit-or-reduce(a, b, a) ;CHECK: node uor-reduce = bit-or-reduce(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node uxor-reduce = bit-xor-reduce(a, b, a) ;CHECK: node uxor-reduce = bit-xor-reduce(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
+
 ;CHECK: Finished Infer Types
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index 2adba2b8..f9f7ac5c 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -30,7 +30,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal-uu(v, UInt(0))
+      v := eq-uu(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir
index bf6f87ab..5713cd43 100644
--- a/test/passes/inline/gcd.fir
+++ b/test/passes/inline/gcd.fir
@@ -30,7 +30,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal-uu(v, UInt(0))
+      v := eq-uu(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index d8197112..bf3eaf01 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -22,12 +22,12 @@ circuit Risc :
     node rai = bits(inst, 15, 8)
     node rbi = bits(inst, 7, 0)
     node T_52 = UInt(0, 1)
-    node T_53 = equal(rai, T_52)
+    node T_53 = eq(rai, T_52)
     node T_54 = UInt(0, 1)
     accessor T_55 = file[rai]
     node ra = mux(T_53, T_54, T_55)
     node T_56 = UInt(0, 1)
-    node T_57 = equal(rbi, T_56)
+    node T_57 = eq(rbi, T_56)
     node T_58 = UInt(0, 1)
     accessor T_59 = file[rbi]
     node rb = mux(T_57, T_58, T_59)
@@ -45,18 +45,18 @@ circuit Risc :
         node T_64 = UInt(0, 1)
         pc := T_64
       else : 
-        node T_65 = equal(add_op, op)
+        node T_65 = eq(add_op, op)
         when T_65 : 
           node T_66 = add-wrap(ra, rb)
           rc := T_66
-        node T_67 = equal(imm_op, op)
+        node T_67 = eq(imm_op, op)
         when T_67 : 
           node T_68 = shl(rai, 8)
           node T_69 = bit-or(T_68, rbi)
           rc := T_69
         out := rc
         node T_70 = UInt(255, 8)
-        node T_71 = equal(rci, T_70)
+        node T_71 = eq(rci, T_70)
         when T_71 : 
           node T_72 = UInt(1, 1)
           valid := T_72
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 1f41cacd..2190d284 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -7,7 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-wrap(x, y)
-      ;CHECK: z@<g:female> := sub-wrap(x@<g:male>, y@<g:male>)
+      ;CHECK: z@<g:female> := sub-wrap-uu(x@<g:male>, y@<g:male>)
    module gcd :
       input a : UInt(16)
       input b : UInt(16)
@@ -20,7 +20,7 @@ circuit top :
       x.init := UInt(0)
       y.init := UInt(42)
       when gt(x, y) :
-      ;CHECK: when gt(x@<g:male>, y@<g:male>) :
+      ;CHECK: when gt-uu(x@<g:male>, y@<g:male>) :
          inst s of subtracter
          ;CHECK: inst s of subtracter@<g:female>
          s.x := x
@@ -37,7 +37,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal(v, UInt(0))
+      v := eq(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir
index f4ad0e05..e7cd8f34 100644
--- a/test/passes/resolve-kinds/gcd.fir
+++ b/test/passes/resolve-kinds/gcd.fir
@@ -32,7 +32,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal(v, UInt(0))
+      v := eq(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
index a659aa07..a5278efd 100644
--- a/test/passes/split-exp/gcd.fir
+++ b/test/passes/split-exp/gcd.fir
@@ -30,7 +30,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal-uu(v, UInt(0))
+      v := eq-uu(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir
index 7a3179bf..ea316bed 100644
--- a/test/passes/to-flo/gcd.fir
+++ b/test/passes/to-flo/gcd.fir
@@ -30,7 +30,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal-uu(v, UInt(0))
+      v := eq-uu(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)