Fixed bug in primop lowering during type inference. Added reduce instructions and renamed concat -> cat, equal -> eq, and added neq and neg

18 files changed, 461 insertions, 402 deletions

diff --git a/TODO b/TODO
index bbe808c4..1c4f2a17 100644
--- a/TODO
+++ b/TODO
@@ -3,14 +3,11 @@
 ================================================
 
 Important things:
-   Include new parser
    
 ======== Update Core ==========
 Change all primops to be strict on data widths
-Merge pull request and update tests
+Update parser and update tests
 on-reset
-Write lowering step for primops
-Add bit-reduce-and etc to primops (Jonathan)
 Add source locaters
 Add Unit Tests for each pass
 
@@ -31,7 +28,7 @@ Well-formed low firrtl
    All things only assigned to once
 
 ======== Other Passes ========
-PrimOp lowering
+Temp Elimination
 
 ======== Consultations ========
 Patrick:
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index d9105430..d4d12400 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -105,6 +105,9 @@ public val SHIFT-LEFT-S-OP = new PrimOp
 public val SHIFT-RIGHT-OP = new PrimOp
 public val SHIFT-RIGHT-U-OP = new PrimOp
 public val SHIFT-RIGHT-S-OP = new PrimOp
+public val NEG-OP = new PrimOp
+public val NEG-U-OP = new PrimOp
+public val NEG-S-OP = new PrimOp
 public val CONVERT-OP = new PrimOp
 public val CONVERT-U-OP = new PrimOp
 public val CONVERT-S-OP = new PrimOp
@@ -115,6 +118,9 @@ public val BIT-XOR-OP = new PrimOp
 public val CONCAT-OP = new PrimOp
 public val BIT-SELECT-OP = new PrimOp
 public val BITS-SELECT-OP = new PrimOp
+public val BIT-AND-REDUCE-OP = new PrimOp
+public val BIT-OR-REDUCE-OP = new PrimOp
+public val BIT-XOR-REDUCE-OP = new PrimOp
 
 public definterface Expression
 public defmulti type (e:Expression) -> Type
diff --git a/src/main/stanza/firrtl-main.stanza b/src/main/stanza/firrtl-main.stanza
index 2e9f056a..92bb066f 100644
--- a/src/main/stanza/firrtl-main.stanza
+++ b/src/main/stanza/firrtl-main.stanza
@@ -7,7 +7,7 @@
 #include("ir-utils.stanza")
 #include("ir-parser.stanza")
 #include("passes.stanza")
-#include("widthsolver.stanza")
+#include("primop.stanza")
 
 defpackage firrtl-main :
    import core
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 16351edd..7d977746 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -7,7 +7,7 @@
 #include("ir-utils.stanza")
 #include("ir-parser.stanza")
 #include("passes.stanza")
-#include("widthsolver.stanza")
+#include("primop.stanza")
 
 defpackage firrtl-main :
    import core
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 1ba52b03..15441950 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -162,9 +162,12 @@ defsyntax firrtl :
    operators[`geq-us] = GREATER-EQ-US-OP
    operators[`geq-su] = GREATER-EQ-SU-OP
    operators[`geq-ss] = GREATER-EQ-SS-OP
-   operators[`equal] = EQUAL-OP
-   operators[`equal-uu] = EQUAL-UU-OP
-   operators[`equal-ss] = EQUAL-SS-OP
+   operators[`eq] = EQUAL-OP
+   operators[`eq-uu] = EQUAL-UU-OP
+   operators[`eq-ss] = EQUAL-SS-OP
+   operators[`neq] = NEQUAL-OP
+   operators[`neq-uu] = NEQUAL-UU-OP
+   operators[`neq-ss] = NEQUAL-SS-OP
    operators[`mux] = MUX-OP
    operators[`mux-uu] = MUX-UU-OP
    operators[`mux-ss] = MUX-SS-OP
@@ -186,13 +189,19 @@ defsyntax firrtl :
    operators[`convert] = CONVERT-OP
    operators[`convert-u] = CONVERT-U-OP
    operators[`convert-s] = CONVERT-S-OP
+   operators[`neg] = NEG-OP
+   operators[`neg-u] = NEG-U-OP
+   operators[`neg-s] = NEG-S-OP
    operators[`bit-not] = BIT-NOT-OP
    operators[`bit-and] = BIT-AND-OP
    operators[`bit-or] = BIT-OR-OP
    operators[`bit-xor] = BIT-XOR-OP
-   operators[`concat] = CONCAT-OP
+   operators[`cat] = CONCAT-OP
    operators[`bit] = BIT-SELECT-OP
    operators[`bits] = BITS-SELECT-OP
+   operators[`bit-and-reduce] = BIT-AND-REDUCE-OP
+   operators[`bit-or-reduce] = BIT-OR-REDUCE-OP
+   operators[`bit-xor-reduce] = BIT-XOR-REDUCE-OP
 
    defrule exp-form :
       exp-form = (UInt (@do ?value:#int ?width:#int)) :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 310c7227..789b94a3 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -95,9 +95,12 @@ defmethod print (o:OutputStream, op:PrimOp) :
       GREATER-EQ-US-OP : "geq-us"
       GREATER-EQ-SU-OP : "geq-su"
       GREATER-EQ-SS-OP : "geq-ss"
-      EQUAL-OP : "equal"
-      EQUAL-UU-OP : "equal-uu"
-      EQUAL-SS-OP : "equal-ss"
+      EQUAL-OP : "eq"
+      EQUAL-UU-OP : "eq-uu"
+      EQUAL-SS-OP : "eq-ss"
+      NEQUAL-OP : "neq"
+      NEQUAL-UU-OP : "neq-uu"
+      NEQUAL-SS-OP : "neq-ss"
       MUX-OP : "mux"
       MUX-UU-OP : "mux-uu"
       MUX-SS-OP : "mux-ss"
@@ -119,13 +122,19 @@ defmethod print (o:OutputStream, op:PrimOp) :
       CONVERT-OP : "convert"
       CONVERT-U-OP : "convert-u"
       CONVERT-S-OP : "convert-s"
+      NEG-OP : "neg"
+      NEG-U-OP : "neg-u"
+      NEG-S-OP : "neg-s"
       BIT-NOT-OP : "bit-not"
       BIT-AND-OP : "bit-and"
       BIT-OR-OP : "bit-or"
       BIT-XOR-OP : "bit-xor"
-      CONCAT-OP : "concat"
+      CONCAT-OP : "cat"
       BIT-SELECT-OP : "bit"
       BITS-SELECT-OP : "bits"
+      BIT-AND-REDUCE-OP : "bit-and-reduce"
+      BIT-OR-REDUCE-OP : "bit-or-reduce"
+      BIT-XOR-REDUCE-OP : "bit-xor-reduce"
    
 defmethod print (o:OutputStream, e:Expression) :
    match(e) :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index b7cce362..8838b323 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -3,7 +3,7 @@ defpackage firrtl/passes :
   import verse
   import firrtl/ir2
   import firrtl/ir-utils
-  import widthsolver
+  import firrtl/primops
   import firrtl-main
 
 ;============== EXCEPTIONS =================================
@@ -384,230 +384,6 @@ defn make-explicit-reset (c:Circuit) :
 ; Type errors are not checked in this pass, as this is
 ;   postponed for a later/earlier pass.
 
-defn lower-primop (e:DoPrim) -> DoPrim :
-   defn u () : UIntType(UnknownWidth())
-   defn s () : SIntType(UnknownWidth())
-   defn u-and (op1:Expression,op2:Expression) : 
-      match(type(op1), type(op2)) :
-         (t1:UIntType, t2:UIntType) : u()
-         (t1:SIntType, t2) : s()
-         (t1, t2:SIntType) : s()
-         (t1, t2) : UnknownType()
-        
-   defn of-type (op:Expression) :
-      match(type(op)) :
-         (t:UIntType) : u()
-         (t:SIntType) : s()
-         (t) : UnknownType()
-
-   ;println-all(["Inferencing primop type: " e])
-   switch {op(e) == _} :
-      ADD-OP           : 
-         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : ADD-UU-OP
-               (t1:UIntType, t2:SIntType) : ADD-US-OP
-               (t1:SIntType, t2:UIntType) : ADD-SU-OP
-               (t1:SIntType, t2:SIntType) : ADD-SS-OP
-      ADD-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
-      ADD-US-OP        : DoPrim(op(e),args(e),consts(e),s())
-      ADD-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
-      ADD-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
-      SUB-UU-OP        : 
-         DoPrim{_,args(e),consts(e),s()} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : SUB-UU-OP
-               (t1:UIntType, t2:SIntType) : SUB-US-OP
-               (t1:SIntType, t2:UIntType) : SUB-SU-OP
-               (t1:SIntType, t2:SIntType) : SUB-SS-OP
-      SUB-US-OP        : DoPrim(op(e),args(e),consts(e),s())
-      SUB-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
-      SUB-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
-      MUL-OP           : 
-         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : MUL-UU-OP
-               (t1:UIntType, t2:SIntType) : MUL-US-OP
-               (t1:SIntType, t2:UIntType) : MUL-SU-OP
-               (t1:SIntType, t2:SIntType) : MUL-SS-OP
-      MUL-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
-      MUL-US-OP        : DoPrim(op(e),args(e),consts(e),s())
-      MUL-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
-      MUL-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
-      DIV-OP           : 
-         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : DIV-UU-OP
-               (t1:UIntType, t2:SIntType) : DIV-US-OP
-               (t1:SIntType, t2:UIntType) : DIV-SU-OP
-               (t1:SIntType, t2:SIntType) : DIV-SS-OP
-      DIV-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
-      DIV-US-OP        : DoPrim(op(e),args(e),consts(e),s())
-      DIV-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
-      DIV-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
-      MOD-OP           : 
-         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : MOD-UU-OP
-               (t1:UIntType, t2:SIntType) : MOD-US-OP
-               (t1:SIntType, t2:UIntType) : MOD-SU-OP
-               (t1:SIntType, t2:SIntType) : MOD-SS-OP
-      MOD-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
-      MOD-US-OP        : DoPrim(op(e),args(e),consts(e),u())
-      MOD-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
-      MOD-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
-      QUO-OP           : 
-         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : QUO-UU-OP
-               (t1:UIntType, t2:SIntType) : QUO-US-OP
-               (t1:SIntType, t2:UIntType) : QUO-SU-OP
-               (t1:SIntType, t2:SIntType) : QUO-SS-OP
-      QUO-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
-      QUO-US-OP        : DoPrim(op(e),args(e),consts(e),s())
-      QUO-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
-      QUO-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
-      REM-OP           : 
-         DoPrim{_,args(e),consts(e),of-type(args(e)[1])} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : REM-UU-OP
-               (t1:UIntType, t2:SIntType) : REM-US-OP
-               (t1:SIntType, t2:UIntType) : REM-SU-OP
-               (t1:SIntType, t2:SIntType) : REM-SS-OP
-      REM-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
-      REM-US-OP        : DoPrim(op(e),args(e),consts(e),s())
-      REM-SU-OP        : DoPrim(op(e),args(e),consts(e),u())
-      REM-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
-      ADD-WRAP-OP      : 
-         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : ADD-WRAP-UU-OP
-               (t1:UIntType, t2:SIntType) : ADD-WRAP-US-OP
-               (t1:SIntType, t2:UIntType) : ADD-WRAP-SU-OP
-               (t1:SIntType, t2:SIntType) : ADD-WRAP-SS-OP
-      ADD-WRAP-UU-OP   : DoPrim(op(e),args(e),consts(e),u())
-      ADD-WRAP-US-OP   : DoPrim(op(e),args(e),consts(e),s())
-      ADD-WRAP-SU-OP   : DoPrim(op(e),args(e),consts(e),s())
-      ADD-WRAP-SS-OP   : DoPrim(op(e),args(e),consts(e),s())
-      SUB-WRAP-OP      : 
-         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : SUB-WRAP-UU-OP
-               (t1:UIntType, t2:SIntType) : SUB-WRAP-US-OP
-               (t1:SIntType, t2:UIntType) : SUB-WRAP-SU-OP
-               (t1:SIntType, t2:SIntType) : SUB-WRAP-SS-OP
-      SUB-WRAP-UU-OP   : DoPrim(op(e),args(e),consts(e),u())
-      SUB-WRAP-US-OP   : DoPrim(op(e),args(e),consts(e),s())
-      SUB-WRAP-SU-OP   : DoPrim(op(e),args(e),consts(e),s())
-      SUB-WRAP-SS-OP   : DoPrim(op(e),args(e),consts(e),s())
-      LESS-OP          : 
-         DoPrim{_,args(e),consts(e),u()} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : LESS-UU-OP
-               (t1:UIntType, t2:SIntType) : LESS-US-OP
-               (t1:SIntType, t2:UIntType) : LESS-SU-OP
-               (t1:SIntType, t2:SIntType) : LESS-SS-OP
-      LESS-UU-OP       : DoPrim(op(e),args(e),consts(e),u())
-      LESS-US-OP       : DoPrim(op(e),args(e),consts(e),u())
-      LESS-SU-OP       : DoPrim(op(e),args(e),consts(e),u())
-      LESS-SS-OP       : DoPrim(op(e),args(e),consts(e),u())
-      LESS-EQ-OP       : 
-         DoPrim{_,args(e),consts(e),u()} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : LESS-EQ-UU-OP
-               (t1:UIntType, t2:SIntType) : LESS-EQ-US-OP
-               (t1:SIntType, t2:UIntType) : LESS-EQ-SU-OP
-               (t1:SIntType, t2:SIntType) : LESS-EQ-SS-OP
-      LESS-EQ-UU-OP    : DoPrim(op(e),args(e),consts(e),u())
-      LESS-EQ-US-OP    : DoPrim(op(e),args(e),consts(e),u())
-      LESS-EQ-SU-OP    : DoPrim(op(e),args(e),consts(e),u())
-      LESS-EQ-SS-OP    : DoPrim(op(e),args(e),consts(e),u())
-      GREATER-OP       : 
-         DoPrim{_,args(e),consts(e),u()} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : GREATER-UU-OP
-               (t1:UIntType, t2:SIntType) : GREATER-US-OP
-               (t1:SIntType, t2:UIntType) : GREATER-SU-OP
-               (t1:SIntType, t2:SIntType) : GREATER-SS-OP
-      GREATER-UU-OP    : DoPrim(op(e),args(e),consts(e),u())
-      GREATER-US-OP    : DoPrim(op(e),args(e),consts(e),u())
-      GREATER-SU-OP    : DoPrim(op(e),args(e),consts(e),u())
-      GREATER-SS-OP    : DoPrim(op(e),args(e),consts(e),u())
-      GREATER-EQ-OP    : 
-         DoPrim{_,args(e),consts(e),u()} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : GREATER-EQ-UU-OP
-               (t1:UIntType, t2:SIntType) : GREATER-EQ-US-OP
-               (t1:SIntType, t2:UIntType) : GREATER-EQ-SU-OP
-               (t1:SIntType, t2:SIntType) : GREATER-EQ-SS-OP
-      GREATER-EQ-UU-OP : DoPrim(op(e),args(e),consts(e),u())
-      GREATER-EQ-US-OP : DoPrim(op(e),args(e),consts(e),u())
-      GREATER-EQ-SU-OP : DoPrim(op(e),args(e),consts(e),u())
-      GREATER-EQ-SS-OP : DoPrim(op(e),args(e),consts(e),u())
-      EQUAL-OP         : 
-         DoPrim{_,args(e),consts(e),u()} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : EQUAL-UU-OP
-               (t1:SIntType, t2:SIntType) : EQUAL-SS-OP
-      EQUAL-UU-OP      : DoPrim(op(e),args(e),consts(e),u())
-      EQUAL-SS-OP      : DoPrim(op(e),args(e),consts(e),u())
-      MUX-OP           : 
-         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
-            match(type(args(e)[0]),type(args(e)[0])) :
-               (t1:UIntType, t2:UIntType) : MUX-UU-OP
-               (t1:SIntType, t2:SIntType) : MUX-SS-OP
-      MUX-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
-      MUX-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
-      PAD-OP           : 
-         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
-            match(type(args(e)[0])) :
-               (t1:UIntType) : PAD-U-OP
-               (t1:SIntType) : PAD-S-OP
-      PAD-U-OP         : DoPrim(op(e),args(e),consts(e),u())
-      PAD-S-OP         : DoPrim(op(e),args(e),consts(e),s())
-      AS-UINT-OP       : 
-         DoPrim{_,args(e),consts(e),u()} $
-            match(type(args(e)[0])) :
-               (t1:UIntType) : AS-UINT-U-OP
-               (t1:SIntType) : AS-UINT-S-OP
-      AS-UINT-U-OP     : DoPrim(op(e),args(e),consts(e),u())
-      AS-UINT-S-OP     : DoPrim(op(e),args(e),consts(e),u())
-      AS-SINT-OP       : 
-         DoPrim{_,args(e),consts(e),s()} $
-            match(type(args(e)[0])) :
-               (t1:UIntType) : AS-SINT-U-OP
-               (t1:SIntType) : AS-SINT-S-OP
-      AS-SINT-U-OP     : DoPrim(op(e),args(e),consts(e),s())
-      AS-SINT-S-OP     : DoPrim(op(e),args(e),consts(e),s())
-      SHIFT-LEFT-OP    : 
-         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
-            match(type(args(e)[0])) :
-               (t1:UIntType) : SHIFT-LEFT-U-OP
-               (t1:SIntType) : SHIFT-LEFT-S-OP
-      SHIFT-LEFT-U-OP  : DoPrim(op(e),args(e),consts(e),u())
-      SHIFT-LEFT-S-OP  : DoPrim(op(e),args(e),consts(e),s())
-      SHIFT-RIGHT-OP   : 
-         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
-            match(type(args(e)[0])) :
-               (t1:UIntType) : SHIFT-RIGHT-U-OP
-               (t1:SIntType) : SHIFT-RIGHT-S-OP
-      SHIFT-RIGHT-U-OP : DoPrim(op(e),args(e),consts(e),u())
-      SHIFT-RIGHT-S-OP : DoPrim(op(e),args(e),consts(e),s())
-      CONVERT-OP       : 
-         DoPrim{_,args(e),consts(e),s()} $
-            match(type(args(e)[0])) :
-               (t1:UIntType) : CONVERT-U-OP
-               (t1:SIntType) : CONVERT-S-OP
-      CONVERT-U-OP     : DoPrim(op(e),args(e),consts(e),s())
-      CONVERT-S-OP     : DoPrim(op(e),args(e),consts(e),s())
-      BIT-NOT-OP       : DoPrim(op(e),args(e),consts(e),u())
-      BIT-AND-OP       : DoPrim(op(e),args(e),consts(e),u())
-      BIT-OR-OP        : DoPrim(op(e),args(e),consts(e),u())
-      BIT-XOR-OP       : DoPrim(op(e),args(e),consts(e),u())
-      CONCAT-OP        : DoPrim(op(e),args(e),consts(e),u())
-      BIT-SELECT-OP    : DoPrim(op(e),args(e),consts(e),u())
-      BITS-SELECT-OP   : DoPrim(op(e),args(e),consts(e),u())
-
 defn type (m:Module) -> Type : 
    BundleType(for p in ports(m) map : to-field(p))
 
@@ -639,7 +415,7 @@ defn infer-exp-types (e:Expression, l:List<KeyValue<Symbol,Type>>) -> Expression
       (e:WSubfield) : WSubfield(exp(e),name(e), bundle-field-type(type(exp(e)),name(e)),gender(e))
       (e:WRegInit) : WRegInit(reg(e),name(e),get-type(name(reg(e) as WRef),l),gender(e))
       (e:WIndex) : WIndex(exp(e),value(e), get-vector-subtype(type(exp(e))),gender(e))
-      (e:DoPrim) : lower-primop(e)
+      (e:DoPrim) : lower-and-type-primop(e)
          ;DoPrim(op(e),args(e),consts(e),get-primop-rettype(e))
       (e:ReadPort) : ReadPort(mem(e),index(e),get-vector-subtype(type(mem(e))),enable(e))
       (e:WritePort) : WritePort(mem(e),index(e),get-vector-subtype(type(mem(e))),enable(e))
@@ -1535,15 +1311,15 @@ defn expand-whens (c:Circuit) -> Circuit :
 ;   widths.
 ; Low FIRRTL Pass.
 
-defstruct VarWidth <: Width :
+public defstruct VarWidth <: Width :
    name: Symbol
-defstruct PlusWidth <: Width :
+public defstruct PlusWidth <: Width :
    arg1 : Width
    arg2 : Width
-defstruct MinusWidth <: Width :
+public defstruct MinusWidth <: Width :
    arg1 : Width
    arg2 : Width
-defstruct MaxWidth <: Width :
+public defstruct MaxWidth <: Width :
    args : List<Width>
 
 public defmulti map<?T> (f: Width -> Width, w:?T&Width) -> T
@@ -1554,20 +1330,20 @@ defmethod map (f: Width -> Width, w:Width) -> Width :
       (w:MinusWidth) : MinusWidth(f(arg1(w)),f(arg2(w)))
       (w) : w
 
-defmethod print (o:OutputStream, w:VarWidth) :
+public defmethod print (o:OutputStream, w:VarWidth) :
    print(o,name(w))
-defmethod print (o:OutputStream, w:MaxWidth) :
+public defmethod print (o:OutputStream, w:MaxWidth) :
    print-all(o,["max" args(w)])
-defmethod print (o:OutputStream, w:PlusWidth) :
+public defmethod print (o:OutputStream, w:PlusWidth) :
    print-all(o,[ arg1(w) " + " arg2(w)])
-defmethod print (o:OutputStream, w:MinusWidth) :
+public defmethod print (o:OutputStream, w:MinusWidth) :
    print-all(o,[ arg1(w) " - " arg2(w)])
 
-definterface Constraint
-defstruct WGeq <: Constraint :
+public definterface Constraint
+public defstruct WGeq <: Constraint :
    loc : Width
    exp : Width
-defmethod print (o:OutputStream, c:WGeq) :
+public defmethod print (o:OutputStream, c:WGeq) :
    print-all(o,[ loc(c) " >= " exp(c)])
 defmethod equal? (w1:Width,w2:Width) -> True|False :
    match(w1,w2) :
@@ -1735,118 +1511,14 @@ defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Int> :
    ;for x in e do : println(x)
    e
    
-defn width! (t:Type) -> Width :
+public defn width! (t:Type) -> Width :
    match(t) :
       (t:UIntType) : width(t)
       (t:SIntType) : width(t)
       (t) : error("No width!")
-defn width! (e:Expression) -> Width : width!(type(e))
+public defn width! (e:Expression) -> Width : width!(type(e))
 
 defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Module:
-   defn prim-type (e:DoPrim,v:Vector<WGeq>) -> Type :
-      defn add-c (w:Width) -> Type:
-         val w* = VarWidth(gensym(`w))
-         add(v,WGeq(w*,w))
-         add(v,WGeq(w,w*))
-         match(type(e)) :
-            (t:UIntType) : UIntType(w*)
-            (t:SIntType) : SIntType(w*)
-            (t) : error("Shouldn't be here")
-      defn wpc (l:List<Expression>,c:List<Int>) :
-         add-c(PlusWidth(width!(l[0]),IntWidth(c[0])))
-      defn wmc (l:List<Expression>,c:List<Int>) :
-         add-c(MinusWidth(width!(l[0]),IntWidth(c[0])))
-      defn maxw (l:List<Expression>) : 
-         add-c(MaxWidth(map(width!,l)))
-      defn cons (ls:List<Expression>) : 
-         val l = width!(ls[0])
-         val r = width!(ls[1])
-         add(v,WGeq(l,r))
-         add(v,WGeq(r,l))
-         add-c(l)
-         add-c(r)
-      defn mp1 (l:List<Expression>) : 
-         add-c(PlusWidth(MaxWidth(list(width!(l[0]),width!(l[1]))),IntWidth(1)))
-      defn sum (l:List<Expression>) : 
-         add-c(PlusWidth(width!(l[0]),width!(l[1])))
-
-      println-all(["Looking at " op(e) " with inputs " args(e)])
-      switch {op(e) == _} :
-         ADD-UU-OP : mp1(args(e))
-         ADD-US-OP : mp1(args(e))
-         ADD-SU-OP : mp1(args(e))
-         ADD-SS-OP : mp1(args(e))
-         SUB-UU-OP : mp1(args(e))
-         SUB-US-OP : mp1(args(e))
-         SUB-SU-OP : mp1(args(e))
-         SUB-SS-OP : mp1(args(e))
-         MUL-UU-OP : sum(args(e))
-         MUL-US-OP : sum(args(e))
-         MUL-SU-OP : sum(args(e))
-         MUL-SS-OP : sum(args(e))
-         ;(p:DIV-UU-OP) : 
-         ;(p:DIV-US-OP) :
-         ;(p:DIV-SU-OP) :
-         ;(p:DIV-SS-OP) :
-         ;(p:MOD-UU-OP) :
-         ;(p:MOD-US-OP) :
-         ;(p:MOD-SU-OP) :
-         ;(p:MOD-SS-OP) :
-         ;(p:QUO-UU-OP) :
-         ;(p:QUO-US-OP) :
-         ;(p:QUO-SU-OP) :
-         ;(p:QUO-SS-OP) :
-         ;(p:REM-UU-OP) :
-         ;(p:REM-US-OP) :
-         ;(p:REM-SU-OP) :
-         ;(p:REM-SS-OP) :
-         ADD-WRAP-UU-OP : maxw(args(e))
-         ADD-WRAP-US-OP : maxw(args(e))
-         ADD-WRAP-SU-OP : maxw(args(e))
-         ADD-WRAP-SS-OP : maxw(args(e))
-         SUB-WRAP-UU-OP : maxw(args(e))
-         SUB-WRAP-US-OP : maxw(args(e))
-         SUB-WRAP-SU-OP : maxw(args(e))
-         SUB-WRAP-SS-OP : maxw(args(e))
-         LESS-UU-OP : add-c(IntWidth(1))
-         LESS-US-OP : add-c(IntWidth(1))
-         LESS-SU-OP : add-c(IntWidth(1))
-         LESS-SS-OP : add-c(IntWidth(1))
-         LESS-EQ-UU-OP : add-c(IntWidth(1))
-         LESS-EQ-US-OP : add-c(IntWidth(1))
-         LESS-EQ-SU-OP : add-c(IntWidth(1))
-         LESS-EQ-SS-OP : add-c(IntWidth(1))
-         GREATER-UU-OP : add-c(IntWidth(1))
-         GREATER-US-OP : add-c(IntWidth(1))
-         GREATER-SU-OP : add-c(IntWidth(1))
-         GREATER-SS-OP : add-c(IntWidth(1))
-         GREATER-EQ-UU-OP : add-c(IntWidth(1))
-         GREATER-EQ-US-OP : add-c(IntWidth(1))
-         GREATER-EQ-SU-OP : add-c(IntWidth(1))
-         GREATER-EQ-SS-OP : add-c(IntWidth(1))
-         EQUAL-UU-OP : add-c(IntWidth(1))
-         EQUAL-SS-OP : add-c(IntWidth(1))
-         MUX-UU-OP : cons(args(e))
-         MUX-SS-OP : cons(args(e))
-         PAD-U-OP : add-c(IntWidth(consts(e)[0]))
-         PAD-S-OP : add-c(IntWidth(consts(e)[0]))
-         AS-UINT-U-OP : add-c(width!(args(e)[0]))
-         AS-UINT-S-OP : add-c(width!(args(e)[0]))
-         AS-SINT-U-OP : add-c(width!(args(e)[0]))
-         AS-SINT-S-OP : add-c(width!(args(e)[0]))
-         SHIFT-LEFT-U-OP : wpc(args(e),consts(e))
-         SHIFT-LEFT-S-OP : wpc(args(e),consts(e))
-         SHIFT-RIGHT-U-OP : wmc(args(e),consts(e))
-         SHIFT-RIGHT-S-OP : wmc(args(e),consts(e))
-         CONVERT-U-OP : add-c(PlusWidth(width!(args(e)[0]),IntWidth(1)))
-         CONVERT-S-OP : add-c(width!(args(e)[0]))
-         BIT-NOT-OP : maxw(args(e))
-         BIT-AND-OP : maxw(args(e))
-         BIT-OR-OP : maxw(args(e))
-         BIT-XOR-OP : maxw(args(e))
-         CONCAT-OP : sum(args(e))
-         BIT-SELECT-OP : add-c(IntWidth(1))
-         BITS-SELECT-OP : add-c(IntWidth(consts(e)[0] - consts(e)[1]))
 
    defn gen-constraints-s (s:Stmt) -> Stmt :
       match(map(gen-constraints-s,s)) :
@@ -1867,7 +1539,7 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
          (e:WRef) : WRef(name(e),h[name(e)],kind(e),gender(e))
          (e:WSubfield) : WSubfield(exp(e),name(e),bundle-field-type(type(exp(e)),name(e)),gender(e))
          (e:WIndex) : error("Shouldn't be here")
-         (e:DoPrim) : DoPrim(op(e),args(e),consts(e),prim-type(e,v))
+         (e:DoPrim) : DoPrim(op(e),args(e),consts(e),primop-gen-constraints(e,v))
          (e:ReadPort) : ReadPort(mem(e),index(e),type(type(mem(e)) as VectorType),enable(e))
          (e:WritePort) : WritePort(mem(e),index(e),type(type(mem(e)) as VectorType),enable(e))
          (e:Register) : Register(type(value(e)),value(e),enable(e))
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza
new file mode 100644
index 00000000..a7fc15ac
--- /dev/null
+++ b/src/main/stanza/primop.stanza
@@ -0,0 +1,353 @@
+defpackage firrtl/primops :
+  import core
+  import verse
+  import firrtl/ir2
+  import firrtl/ir-utils
+  import firrtl/passes
+
+public defn lower-and-type-primop (e:DoPrim) -> DoPrim :
+   defn u () : UIntType(UnknownWidth())
+   defn s () : SIntType(UnknownWidth())
+   defn u-and (op1:Expression,op2:Expression) : 
+      match(type(op1), type(op2)) :
+         (t1:UIntType, t2:UIntType) : u()
+         (t1:SIntType, t2) : s()
+         (t1, t2:SIntType) : s()
+         (t1, t2) : UnknownType()
+        
+   defn of-type (op:Expression) :
+      match(type(op)) :
+         (t:UIntType) : u()
+         (t:SIntType) : s()
+         (t) : UnknownType()
+
+   println-all(["Inferencing primop type: " e])
+   switch {op(e) == _} :
+      ADD-OP           : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : ADD-UU-OP
+               (t1:UIntType, t2:SIntType) : ADD-US-OP
+               (t1:SIntType, t2:UIntType) : ADD-SU-OP
+               (t1:SIntType, t2:SIntType) : ADD-SS-OP
+      ADD-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      ADD-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      ADD-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      ADD-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      SUB-OP           : 
+         DoPrim{_,args(e),consts(e),s()} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : SUB-UU-OP
+               (t1:UIntType, t2:SIntType) : SUB-US-OP
+               (t1:SIntType, t2:UIntType) : SUB-SU-OP
+               (t1:SIntType, t2:SIntType) : SUB-SS-OP
+      SUB-UU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      SUB-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      SUB-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      SUB-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      MUL-OP           : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : MUL-UU-OP
+               (t1:UIntType, t2:SIntType) : MUL-US-OP
+               (t1:SIntType, t2:UIntType) : MUL-SU-OP
+               (t1:SIntType, t2:SIntType) : MUL-SS-OP
+      MUL-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      MUL-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      MUL-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      MUL-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      DIV-OP           : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : DIV-UU-OP
+               (t1:UIntType, t2:SIntType) : DIV-US-OP
+               (t1:SIntType, t2:UIntType) : DIV-SU-OP
+               (t1:SIntType, t2:SIntType) : DIV-SS-OP
+      DIV-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      DIV-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      DIV-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      DIV-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      MOD-OP           : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : MOD-UU-OP
+               (t1:UIntType, t2:SIntType) : MOD-US-OP
+               (t1:SIntType, t2:UIntType) : MOD-SU-OP
+               (t1:SIntType, t2:SIntType) : MOD-SS-OP
+      MOD-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      MOD-US-OP        : DoPrim(op(e),args(e),consts(e),u())
+      MOD-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      MOD-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      QUO-OP           : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : QUO-UU-OP
+               (t1:UIntType, t2:SIntType) : QUO-US-OP
+               (t1:SIntType, t2:UIntType) : QUO-SU-OP
+               (t1:SIntType, t2:SIntType) : QUO-SS-OP
+      QUO-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      QUO-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      QUO-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      QUO-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      REM-OP           : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : REM-UU-OP
+               (t1:UIntType, t2:SIntType) : REM-US-OP
+               (t1:SIntType, t2:UIntType) : REM-SU-OP
+               (t1:SIntType, t2:SIntType) : REM-SS-OP
+      REM-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      REM-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      REM-SU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      REM-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      ADD-WRAP-OP      : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : ADD-WRAP-UU-OP
+               (t1:UIntType, t2:SIntType) : ADD-WRAP-US-OP
+               (t1:SIntType, t2:UIntType) : ADD-WRAP-SU-OP
+               (t1:SIntType, t2:SIntType) : ADD-WRAP-SS-OP
+      ADD-WRAP-UU-OP   : DoPrim(op(e),args(e),consts(e),u())
+      ADD-WRAP-US-OP   : DoPrim(op(e),args(e),consts(e),s())
+      ADD-WRAP-SU-OP   : DoPrim(op(e),args(e),consts(e),s())
+      ADD-WRAP-SS-OP   : DoPrim(op(e),args(e),consts(e),s())
+      SUB-WRAP-OP      : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : SUB-WRAP-UU-OP
+               (t1:UIntType, t2:SIntType) : SUB-WRAP-US-OP
+               (t1:SIntType, t2:UIntType) : SUB-WRAP-SU-OP
+               (t1:SIntType, t2:SIntType) : SUB-WRAP-SS-OP
+      SUB-WRAP-UU-OP   : DoPrim(op(e),args(e),consts(e),u())
+      SUB-WRAP-US-OP   : DoPrim(op(e),args(e),consts(e),s())
+      SUB-WRAP-SU-OP   : DoPrim(op(e),args(e),consts(e),s())
+      SUB-WRAP-SS-OP   : DoPrim(op(e),args(e),consts(e),s())
+      LESS-OP          : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : LESS-UU-OP
+               (t1:UIntType, t2:SIntType) : LESS-US-OP
+               (t1:SIntType, t2:UIntType) : LESS-SU-OP
+               (t1:SIntType, t2:SIntType) : LESS-SS-OP
+      LESS-UU-OP       : DoPrim(op(e),args(e),consts(e),u())
+      LESS-US-OP       : DoPrim(op(e),args(e),consts(e),u())
+      LESS-SU-OP       : DoPrim(op(e),args(e),consts(e),u())
+      LESS-SS-OP       : DoPrim(op(e),args(e),consts(e),u())
+      LESS-EQ-OP       : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : LESS-EQ-UU-OP
+               (t1:UIntType, t2:SIntType) : LESS-EQ-US-OP
+               (t1:SIntType, t2:UIntType) : LESS-EQ-SU-OP
+               (t1:SIntType, t2:SIntType) : LESS-EQ-SS-OP
+      LESS-EQ-UU-OP    : DoPrim(op(e),args(e),consts(e),u())
+      LESS-EQ-US-OP    : DoPrim(op(e),args(e),consts(e),u())
+      LESS-EQ-SU-OP    : DoPrim(op(e),args(e),consts(e),u())
+      LESS-EQ-SS-OP    : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-OP       : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : GREATER-UU-OP
+               (t1:UIntType, t2:SIntType) : GREATER-US-OP
+               (t1:SIntType, t2:UIntType) : GREATER-SU-OP
+               (t1:SIntType, t2:SIntType) : GREATER-SS-OP
+      GREATER-UU-OP    : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-US-OP    : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-SU-OP    : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-SS-OP    : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-EQ-OP    : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : GREATER-EQ-UU-OP
+               (t1:UIntType, t2:SIntType) : GREATER-EQ-US-OP
+               (t1:SIntType, t2:UIntType) : GREATER-EQ-SU-OP
+               (t1:SIntType, t2:SIntType) : GREATER-EQ-SS-OP
+      GREATER-EQ-UU-OP : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-EQ-US-OP : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-EQ-SU-OP : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-EQ-SS-OP : DoPrim(op(e),args(e),consts(e),u())
+      EQUAL-OP         : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : EQUAL-UU-OP
+               (t1:SIntType, t2:SIntType) : EQUAL-SS-OP
+      EQUAL-UU-OP      : DoPrim(op(e),args(e),consts(e),u())
+      EQUAL-SS-OP      : DoPrim(op(e),args(e),consts(e),u())
+      NEQUAL-OP         : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : NEQUAL-UU-OP
+               (t1:SIntType, t2:SIntType) : NEQUAL-SS-OP
+      NEQUAL-UU-OP      : DoPrim(op(e),args(e),consts(e),u())
+      NEQUAL-SS-OP      : DoPrim(op(e),args(e),consts(e),u())
+      MUX-OP           : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
+            match(type(args(e)[0]),type(args(e)[1])) :
+               (t1:UIntType, t2:UIntType) : MUX-UU-OP
+               (t1:SIntType, t2:SIntType) : MUX-SS-OP
+      MUX-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      MUX-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      PAD-OP           : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : PAD-U-OP
+               (t1:SIntType) : PAD-S-OP
+      PAD-U-OP         : DoPrim(op(e),args(e),consts(e),u())
+      PAD-S-OP         : DoPrim(op(e),args(e),consts(e),s())
+      AS-UINT-OP       : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : AS-UINT-U-OP
+               (t1:SIntType) : AS-UINT-S-OP
+      AS-UINT-U-OP     : DoPrim(op(e),args(e),consts(e),u())
+      AS-UINT-S-OP     : DoPrim(op(e),args(e),consts(e),u())
+      AS-SINT-OP       : 
+         DoPrim{_,args(e),consts(e),s()} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : AS-SINT-U-OP
+               (t1:SIntType) : AS-SINT-S-OP
+      AS-SINT-U-OP     : DoPrim(op(e),args(e),consts(e),s())
+      AS-SINT-S-OP     : DoPrim(op(e),args(e),consts(e),s())
+      SHIFT-LEFT-OP    : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : SHIFT-LEFT-U-OP
+               (t1:SIntType) : SHIFT-LEFT-S-OP
+      SHIFT-LEFT-U-OP  : DoPrim(op(e),args(e),consts(e),u())
+      SHIFT-LEFT-S-OP  : DoPrim(op(e),args(e),consts(e),s())
+      SHIFT-RIGHT-OP   : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : SHIFT-RIGHT-U-OP
+               (t1:SIntType) : SHIFT-RIGHT-S-OP
+      SHIFT-RIGHT-U-OP : DoPrim(op(e),args(e),consts(e),u())
+      SHIFT-RIGHT-S-OP : DoPrim(op(e),args(e),consts(e),s())
+      CONVERT-OP       : 
+         DoPrim{_,args(e),consts(e),s()} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : CONVERT-U-OP
+               (t1:SIntType) : CONVERT-S-OP
+      CONVERT-U-OP     : DoPrim(op(e),args(e),consts(e),s())
+      CONVERT-S-OP     : DoPrim(op(e),args(e),consts(e),s())
+      NEG-OP         : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : NEG-U-OP
+               (t1:SIntType) : NEG-S-OP
+      NEG-U-OP         : DoPrim(op(e),args(e),consts(e),u())
+      NEG-S-OP         : DoPrim(op(e),args(e),consts(e),u())
+      BIT-NOT-OP       : DoPrim(op(e),args(e),consts(e),u())
+      BIT-AND-OP       : DoPrim(op(e),args(e),consts(e),u())
+      BIT-OR-OP        : DoPrim(op(e),args(e),consts(e),u())
+      BIT-XOR-OP       : DoPrim(op(e),args(e),consts(e),u())
+      CONCAT-OP        : DoPrim(op(e),args(e),consts(e),u())
+      BIT-SELECT-OP    : DoPrim(op(e),args(e),consts(e),u())
+      BITS-SELECT-OP   : DoPrim(op(e),args(e),consts(e),u())
+      BIT-AND-REDUCE-OP: DoPrim(op(e),args(e),consts(e),u())
+      BIT-OR-REDUCE-OP : DoPrim(op(e),args(e),consts(e),u())
+      BIT-XOR-REDUCE-OP: DoPrim(op(e),args(e),consts(e),u())
+
+public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type :
+   defn add-c (w:Width) -> Type:
+      val w* = VarWidth(gensym(`w))
+      add(v,WGeq(w*,w))
+      add(v,WGeq(w,w*))
+      match(type(e)) :
+         (t:UIntType) : UIntType(w*)
+         (t:SIntType) : SIntType(w*)
+         (t) : error("Shouldn't be here")
+   defn wpc (l:List<Expression>,c:List<Int>) :
+      add-c(PlusWidth(width!(l[0]),IntWidth(c[0])))
+   defn wmc (l:List<Expression>,c:List<Int>) :
+      add-c(MinusWidth(width!(l[0]),IntWidth(c[0])))
+   defn maxw (l:List<Expression>) : 
+      add-c(MaxWidth(map(width!,l)))
+   defn cons (ls:List<Expression>) : 
+      val l = width!(ls[0])
+      val r = width!(ls[1])
+      add(v,WGeq(l,r))
+      add(v,WGeq(r,l))
+      add-c(l)
+      add-c(r)
+   defn mp1 (l:List<Expression>) : 
+      add-c(PlusWidth(MaxWidth(list(width!(l[0]),width!(l[1]))),IntWidth(1)))
+   defn sum (l:List<Expression>) : 
+      add-c(PlusWidth(width!(l[0]),width!(l[1])))
+
+   println-all(["Looking at " op(e) " with inputs " args(e)])
+   switch {op(e) == _} :
+      ADD-UU-OP : mp1(args(e))
+      ADD-US-OP : mp1(args(e))
+      ADD-SU-OP : mp1(args(e))
+      ADD-SS-OP : mp1(args(e))
+      SUB-UU-OP : mp1(args(e))
+      SUB-US-OP : mp1(args(e))
+      SUB-SU-OP : mp1(args(e))
+      SUB-SS-OP : mp1(args(e))
+      MUL-UU-OP : sum(args(e))
+      MUL-US-OP : sum(args(e))
+      MUL-SU-OP : sum(args(e))
+      MUL-SS-OP : sum(args(e))
+      ;(p:DIV-UU-OP) : 
+      ;(p:DIV-US-OP) :
+      ;(p:DIV-SU-OP) :
+      ;(p:DIV-SS-OP) :
+      ;(p:MOD-UU-OP) :
+      ;(p:MOD-US-OP) :
+      ;(p:MOD-SU-OP) :
+      ;(p:MOD-SS-OP) :
+      ;(p:QUO-UU-OP) :
+      ;(p:QUO-US-OP) :
+      ;(p:QUO-SU-OP) :
+      ;(p:QUO-SS-OP) :
+      ;(p:REM-UU-OP) :
+      ;(p:REM-US-OP) :
+      ;(p:REM-SU-OP) :
+      ;(p:REM-SS-OP) :
+      ADD-WRAP-UU-OP : maxw(args(e))
+      ADD-WRAP-US-OP : maxw(args(e))
+      ADD-WRAP-SU-OP : maxw(args(e))
+      ADD-WRAP-SS-OP : maxw(args(e))
+      SUB-WRAP-UU-OP : maxw(args(e))
+      SUB-WRAP-US-OP : maxw(args(e))
+      SUB-WRAP-SU-OP : maxw(args(e))
+      SUB-WRAP-SS-OP : maxw(args(e))
+      LESS-UU-OP : add-c(IntWidth(1))
+      LESS-US-OP : add-c(IntWidth(1))
+      LESS-SU-OP : add-c(IntWidth(1))
+      LESS-SS-OP : add-c(IntWidth(1))
+      LESS-EQ-UU-OP : add-c(IntWidth(1))
+      LESS-EQ-US-OP : add-c(IntWidth(1))
+      LESS-EQ-SU-OP : add-c(IntWidth(1))
+      LESS-EQ-SS-OP : add-c(IntWidth(1))
+      GREATER-UU-OP : add-c(IntWidth(1))
+      GREATER-US-OP : add-c(IntWidth(1))
+      GREATER-SU-OP : add-c(IntWidth(1))
+      GREATER-SS-OP : add-c(IntWidth(1))
+      GREATER-EQ-UU-OP : add-c(IntWidth(1))
+      GREATER-EQ-US-OP : add-c(IntWidth(1))
+      GREATER-EQ-SU-OP : add-c(IntWidth(1))
+      GREATER-EQ-SS-OP : add-c(IntWidth(1))
+      EQUAL-UU-OP : add-c(IntWidth(1))
+      EQUAL-SS-OP : add-c(IntWidth(1))
+      MUX-UU-OP : cons(args(e))
+      MUX-SS-OP : cons(args(e))
+      PAD-U-OP : add-c(IntWidth(consts(e)[0]))
+      PAD-S-OP : add-c(IntWidth(consts(e)[0]))
+      AS-UINT-U-OP : add-c(width!(args(e)[0]))
+      AS-UINT-S-OP : add-c(width!(args(e)[0]))
+      AS-SINT-U-OP : add-c(width!(args(e)[0]))
+      AS-SINT-S-OP : add-c(width!(args(e)[0]))
+      SHIFT-LEFT-U-OP : wpc(args(e),consts(e))
+      SHIFT-LEFT-S-OP : wpc(args(e),consts(e))
+      SHIFT-RIGHT-U-OP : wmc(args(e),consts(e))
+      SHIFT-RIGHT-S-OP : wmc(args(e),consts(e))
+      CONVERT-U-OP : add-c(PlusWidth(width!(args(e)[0]),IntWidth(1)))
+      CONVERT-S-OP : add-c(width!(args(e)[0]))
+      BIT-NOT-OP : maxw(args(e))
+      BIT-AND-OP : maxw(args(e))
+      BIT-OR-OP : maxw(args(e))
+      BIT-XOR-OP : maxw(args(e))
+      CONCAT-OP : sum(args(e))
+      BIT-SELECT-OP : add-c(IntWidth(1))
+      BITS-SELECT-OP : add-c(IntWidth(consts(e)[0] - consts(e)[1]))
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index f3754a32..e00dd9c2 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -16,10 +16,10 @@ circuit top :
       ; CHECK: wire b$x : UInt(32)
       ; CHECK: wire b$y : UInt(32)
       ; CHECK: b$x := a$0$x
-      ; CHECK: when equal-uu(i, UInt(1)) :
+      ; CHECK: when eq-uu(i, UInt(1)) :
       ; CHECK:    b$x := a$1$x
       ; CHECK: a$0$y := b$y
-      ; CHECK: when equal-uu(i, UInt(1)) :
+      ; CHECK: when eq-uu(i, UInt(1)) :
       ; CHECK:    a$1$y := b$y
       j := b
       
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index ea134c2f..aa43644c 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -7,7 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-wrap(x, y)
-      ;CHECK: z@<t:UInt> := sub-wrap(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
+      ;CHECK: z@<t:UInt> := sub-wrap-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
    module gcd :
       input a : UInt(16)
       input b : UInt(16)
@@ -20,7 +20,7 @@ circuit top :
       x.init := UInt(0)
       y.init := UInt(42)
       when gt(x, y) :
-      ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
+      ;CHECK: when gt-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
          ;CHECK: inst s of subtracter@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt(1)@<t:UInt>}>
          s.x := x
@@ -38,8 +38,8 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal(v, UInt(0))
-      ;CHECK: v@<t:UInt> := equal(v@<t:UInt>, UInt(0))@<t:UInt>
+      v := eq(v, UInt(0))
+      ;CHECK: v@<t:UInt> := eq-uu(v@<t:UInt>, UInt(0))@<t:UInt>
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index 7e7342ae..2c37f361 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -9,120 +9,133 @@ circuit top :
       wire d : SInt(8)
       wire e : UInt(1)
 
-      node vadd = add(a, c)    ;CHECK: node vadd = add(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vadd = add(a, c)    ;CHECK: node vadd = add-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wadd-uu = add-uu(a, b) ;CHECK: node wadd-uu = add-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xadd-us = add-us(a, d) ;CHECK: node xadd-us = add-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node yadd-su = add-su(c, b) ;CHECK: node yadd-su = add-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zadd-ss = add-ss(c, d) ;CHECK: node zadd-ss = add-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vsub = sub(a, c)    ;CHECK: node vsub = sub(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vsub = sub(a, c)    ;CHECK: node vsub = sub-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wsub-uu = sub-uu(a, b) ;CHECK: node wsub-uu = sub-uu(a@<t:UInt>, b@<t:UInt>)@<t:SInt>
       node xsub-us = sub-us(a, d) ;CHECK: node xsub-us = sub-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node ysub-su = sub-su(c, b) ;CHECK: node ysub-su = sub-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zsub-ss = sub-ss(c, d) ;CHECK: node zsub-ss = sub-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vmul = mul(a, c)    ;CHECK: node vmul = mul(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vmul = mul(a, c)    ;CHECK: node vmul = mul-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wmul-uu = mul-uu(a, b) ;CHECK: node wmul-uu = mul-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xmul-us = mul-us(a, d) ;CHECK: node xmul-us = mul-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node ymul-su = mul-su(c, b) ;CHECK: node ymul-su = mul-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zmul-ss = mul-ss(c, d) ;CHECK: node zmul-ss = mul-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vdiv = div(a, c)    ;CHECK: node vdiv = div(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vdiv = div(a, c)    ;CHECK: node vdiv = div-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wdiv-uu = div-uu(a, b) ;CHECK: node wdiv-uu = div-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xdiv-us = div-us(a, d) ;CHECK: node xdiv-us = div-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node ydiv-su = div-su(c, b) ;CHECK: node ydiv-su = div-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zdiv-ss = div-ss(c, d) ;CHECK: node zdiv-ss = div-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vmod = mod(a, c)    ;CHECK: node vmod = mod(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+      node vmod = mod(a, c)    ;CHECK: node vmod = mod-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wmod-uu = mod-uu(a, b) ;CHECK: node wmod-uu = mod-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xmod-us = mod-us(a, d) ;CHECK: node xmod-us = mod-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
       node ymod-su = mod-su(c, b) ;CHECK: node ymod-su = mod-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zmod-ss = mod-ss(c, d) ;CHECK: node zmod-ss = mod-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vquo = quo(a, c)    ;CHECK: node vquo = quo(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vquo = quo(a, c)    ;CHECK: node vquo = quo-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wquo-uu = quo-uu(a, b) ;CHECK: node wquo-uu = quo-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xquo-us = quo-us(a, d) ;CHECK: node xquo-us = quo-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node yquo-su = quo-su(c, b) ;CHECK: node yquo-su = quo-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zquo-ss = quo-ss(c, d) ;CHECK: node zquo-ss = quo-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vrem = rem(a, c)    ;CHECK: node vrem = rem(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vrem = rem(a, c)    ;CHECK: node vrem = rem-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wrem-uu = rem-uu(a, b) ;CHECK: node wrem-uu = rem-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xrem-us = rem-us(a, d) ;CHECK: node xrem-us = rem-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node yrem-su = rem-su(c, b) ;CHECK: node yrem-su = rem-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zrem-ss = rem-ss(c, d) ;CHECK: node zrem-ss = rem-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vadd-wrap = add-wrap(a, c)    ;CHECK: node vadd-wrap = add-wrap(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vadd-wrap = add-wrap(a, c)    ;CHECK: node vadd-wrap = add-wrap-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wadd-wrap-uu = add-wrap-uu(a, b) ;CHECK: node wadd-wrap-uu = add-wrap-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xadd-wrap-us = add-wrap-us(a, d) ;CHECK: node xadd-wrap-us = add-wrap-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node yadd-wrap-su = add-wrap-su(c, b) ;CHECK: node yadd-wrap-su = add-wrap-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zadd-wrap-ss = add-wrap-ss(c, d) ;CHECK: node zadd-wrap-ss = add-wrap-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vsub-wrap = sub-wrap(a, c)    ;CHECK: node vsub-wrap = sub-wrap(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
+      node vsub-wrap = sub-wrap(a, c)    ;CHECK: node vsub-wrap = sub-wrap-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wsub-wrap-uu = sub-wrap-uu(a, b) ;CHECK: node wsub-wrap-uu = sub-wrap-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xsub-wrap-us = sub-wrap-us(a, d) ;CHECK: node xsub-wrap-us = sub-wrap-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt>
       node ysub-wrap-su = sub-wrap-su(c, b) ;CHECK: node ysub-wrap-su = sub-wrap-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt>
       node zsub-wrap-ss = sub-wrap-ss(c, d) ;CHECK: node zsub-wrap-ss = sub-wrap-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vlt = lt(a, c)    ;CHECK: node vlt = lt(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+      node vlt = lt(a, c)    ;CHECK: node vlt = lt-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wlt-uu = lt-uu(a, b) ;CHECK: node wlt-uu = lt-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xlt-us = lt-us(a, d) ;CHECK: node xlt-us = lt-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
       node ylt-su = lt-su(c, b) ;CHECK: node ylt-su = lt-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zlt-ss = lt-ss(c, d) ;CHECK: node zlt-ss = lt-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vleq = leq(a, c)    ;CHECK: node vleq = leq(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+      node vleq = leq(a, c)    ;CHECK: node vleq = leq-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wleq-uu = leq-uu(a, b) ;CHECK: node wleq-uu = leq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xleq-us = leq-us(a, d) ;CHECK: node xleq-us = leq-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
       node yleq-su = leq-su(c, b) ;CHECK: node yleq-su = leq-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zleq-ss = leq-ss(c, d) ;CHECK: node zleq-ss = leq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vgt = gt(a, c)    ;CHECK: node vgt = gt(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+      node vgt = gt(a, c)    ;CHECK: node vgt = gt-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wgt-uu = gt-uu(a, b) ;CHECK: node wgt-uu = gt-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xgt-us = gt-us(a, d) ;CHECK: node xgt-us = gt-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
       node ygt-su = gt-su(c, b) ;CHECK: node ygt-su = gt-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zgt-ss = gt-ss(c, d) ;CHECK: node zgt-ss = gt-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vgeq = geq(a, c)    ;CHECK: node vgeq = geq(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
+      node vgeq = geq(a, c)    ;CHECK: node vgeq = geq-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt>
       node wgeq-uu = geq-uu(a, b) ;CHECK: node wgeq-uu = geq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node xgeq-us = geq-us(a, d) ;CHECK: node xgeq-us = geq-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt>
       node ygeq-su = geq-su(c, b) ;CHECK: node ygeq-su = geq-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt>
       node zgeq-ss = geq-ss(c, d) ;CHECK: node zgeq-ss = geq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vequal = equal(a, b)    ;CHECK: node vequal = equal(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node wequal-uu = equal-uu(a, b) ;CHECK: node wequal-uu = equal-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node zequal-ss = equal-ss(c, d) ;CHECK: node zequal-ss = equal-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
+      node vneq = neq(a, b)    ;CHECK: node vneq = neq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node wneq-uu = neq-uu(a, b) ;CHECK: node wneq-uu = neq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node zneq-ss = neq-ss(c, d) ;CHECK: node zneq-ss = neq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
    
-      node vmux = mux(e, a, b)    ;CHECK: node vmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node veq = eq(a, b)    ;CHECK: node veq = eq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node weq-uu = eq-uu(a, b) ;CHECK: node weq-uu = eq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node zeq-ss = eq-ss(c, d) ;CHECK: node zeq-ss = eq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt>
+   
+      node vmux = mux(e, a, b)    ;CHECK: node vmux = mux-uu(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node wmux-uu = mux-uu(e, a, b) ;CHECK: node wmux-uu = mux-uu(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node zmux-ss = mux-ss(e, c, d) ;CHECK: node zmux-ss = mux-ss(e@<t:UInt>, c@<t:SInt>, d@<t:SInt>)@<t:SInt>
    
-      node vpad = pad(a, 10)   ;CHECK: node vpad = pad(a@<t:UInt>, 10)@<t:UInt>
+      node vpad = pad(a, 10)   ;CHECK: node vpad = pad-u(a@<t:UInt>, 10)@<t:UInt>
       node wpad-u = pad-u(a, 10) ;CHECK: node wpad-u = pad-u(a@<t:UInt>, 10)@<t:UInt>
       node zpad-s = pad-s(c, 10) ;CHECK: node zpad-s = pad-s(c@<t:SInt>, 10)@<t:SInt>
    
-      node vas-UInt = as-UInt(d)   ;CHECK: node vas-UInt = as-UInt(d@<t:SInt>)@<t:UInt>
+      node vas-UInt = as-UInt(d)   ;CHECK: node vas-UInt = as-UInt-s(d@<t:SInt>)@<t:UInt>
       node was-UInt-u = as-UInt-u(a) ;CHECK: node was-UInt-u = as-UInt-u(a@<t:UInt>)@<t:UInt>
       node zas-UInt-s = as-UInt-s(c) ;CHECK: node zas-UInt-s = as-UInt-s(c@<t:SInt>)@<t:UInt>
    
-      node vas-SInt = as-SInt(a)   ;CHECK: node vas-SInt = as-SInt(a@<t:UInt>)@<t:SInt>
+      node vas-SInt = as-SInt(a)   ;CHECK: node vas-SInt = as-SInt-u(a@<t:UInt>)@<t:SInt>
       node was-SInt-u = as-SInt-u(a) ;CHECK: node was-SInt-u = as-SInt-u(a@<t:UInt>)@<t:SInt>
       node zas-SInt-s = as-SInt-s(c) ;CHECK: node zas-SInt-s = as-SInt-s(c@<t:SInt>)@<t:SInt>
    
-      node vshl = shl(a, 10)   ;CHECK: node vshl = shl(a@<t:UInt>, 10)@<t:UInt>
+      node vshl = shl(a, 10)   ;CHECK: node vshl = shl-u(a@<t:UInt>, 10)@<t:UInt>
       node wshl-u = shl-u(a, 10) ;CHECK: node wshl-u = shl-u(a@<t:UInt>, 10)@<t:UInt>
       node zshl-s = shl-s(c, 10) ;CHECK: node zshl-s = shl-s(c@<t:SInt>, 10)@<t:SInt>
    
-      node vshr = shr(a, 10)   ;CHECK: node vshr = shr(a@<t:UInt>, 10)@<t:UInt>
+      node vshr = shr(a, 10)   ;CHECK: node vshr = shr-u(a@<t:UInt>, 10)@<t:UInt>
       node wshr-u = shr-u(a, 10) ;CHECK: node wshr-u = shr-u(a@<t:UInt>, 10)@<t:UInt>
       node zshr-s = shr-s(c, 10) ;CHECK: node zshr-s = shr-s(c@<t:SInt>, 10)@<t:SInt>
    
-      node vconvert = convert(a)   ;CHECK: node vconvert = convert(a@<t:UInt>)@<t:SInt>
+      node vconvert = convert(a)   ;CHECK: node vconvert = convert-u(a@<t:UInt>)@<t:SInt>
       node wconvert-u = convert-u(a) ;CHECK: node wconvert-u = convert-u(a@<t:UInt>)@<t:SInt>
       node zconvert-s = convert-s(c) ;CHECK: node zconvert-s = convert-s(c@<t:SInt>)@<t:SInt>
    
+      node vneg = neg(a)   ;CHECK: node vneg = neg-u(a@<t:UInt>)@<t:UInt>
+      node wneg-u = neg-u(a) ;CHECK: node wneg-u = neg-u(a@<t:UInt>)@<t:UInt>
+      node zneg-s = neg-s(c) ;CHECK: node zneg-s = neg-s(c@<t:SInt>)@<t:UInt>
+   
       node uand = bit-and(a, b) ;CHECK: node uand = bit-and(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node vor = bit-or(a, b)  ;CHECK: node vor = bit-or(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node wxor = bit-xor(a, b) ;CHECK: node wxor = bit-xor(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
-      node xconcat = concat(a, b) ;CHECK: node xconcat = concat(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
+      node xcat = cat(a, b) ;CHECK: node xcat = cat(a@<t:UInt>, b@<t:UInt>)@<t:UInt>
       node ybit = bit(a, 0) ;CHECK: node ybit = bit(a@<t:UInt>, 0)@<t:UInt>
       node zbits = bits(a, 2, 0) ;CHECK: node zbits = bits(a@<t:UInt>, 2, 0)@<t:UInt>
+
+      node uand-reduce = bit-and-reduce(a, b, a) ;CHECK: node uand-reduce = bit-and-reduce(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node uor-reduce = bit-or-reduce(a, b, a) ;CHECK: node uor-reduce = bit-or-reduce(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
+      node uxor-reduce = bit-xor-reduce(a, b, a) ;CHECK: node uxor-reduce = bit-xor-reduce(a@<t:UInt>, b@<t:UInt>, a@<t:UInt>)@<t:UInt>
+
 ;CHECK: Finished Infer Types
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index 2adba2b8..f9f7ac5c 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -30,7 +30,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal-uu(v, UInt(0))
+      v := eq-uu(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir
index bf6f87ab..5713cd43 100644
--- a/test/passes/inline/gcd.fir
+++ b/test/passes/inline/gcd.fir
@@ -30,7 +30,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal-uu(v, UInt(0))
+      v := eq-uu(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index d8197112..bf3eaf01 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -22,12 +22,12 @@ circuit Risc :
     node rai = bits(inst, 15, 8)
     node rbi = bits(inst, 7, 0)
     node T_52 = UInt(0, 1)
-    node T_53 = equal(rai, T_52)
+    node T_53 = eq(rai, T_52)
     node T_54 = UInt(0, 1)
     accessor T_55 = file[rai]
     node ra = mux(T_53, T_54, T_55)
     node T_56 = UInt(0, 1)
-    node T_57 = equal(rbi, T_56)
+    node T_57 = eq(rbi, T_56)
     node T_58 = UInt(0, 1)
     accessor T_59 = file[rbi]
     node rb = mux(T_57, T_58, T_59)
@@ -45,18 +45,18 @@ circuit Risc :
         node T_64 = UInt(0, 1)
         pc := T_64
       else : 
-        node T_65 = equal(add_op, op)
+        node T_65 = eq(add_op, op)
         when T_65 : 
           node T_66 = add-wrap(ra, rb)
           rc := T_66
-        node T_67 = equal(imm_op, op)
+        node T_67 = eq(imm_op, op)
         when T_67 : 
           node T_68 = shl(rai, 8)
           node T_69 = bit-or(T_68, rbi)
           rc := T_69
         out := rc
         node T_70 = UInt(255, 8)
-        node T_71 = equal(rci, T_70)
+        node T_71 = eq(rci, T_70)
         when T_71 : 
           node T_72 = UInt(1, 1)
           valid := T_72
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 1f41cacd..2190d284 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -7,7 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-wrap(x, y)
-      ;CHECK: z@<g:female> := sub-wrap(x@<g:male>, y@<g:male>)
+      ;CHECK: z@<g:female> := sub-wrap-uu(x@<g:male>, y@<g:male>)
    module gcd :
       input a : UInt(16)
       input b : UInt(16)
@@ -20,7 +20,7 @@ circuit top :
       x.init := UInt(0)
       y.init := UInt(42)
       when gt(x, y) :
-      ;CHECK: when gt(x@<g:male>, y@<g:male>) :
+      ;CHECK: when gt-uu(x@<g:male>, y@<g:male>) :
          inst s of subtracter
          ;CHECK: inst s of subtracter@<g:female>
          s.x := x
@@ -37,7 +37,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal(v, UInt(0))
+      v := eq(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir
index f4ad0e05..e7cd8f34 100644
--- a/test/passes/resolve-kinds/gcd.fir
+++ b/test/passes/resolve-kinds/gcd.fir
@@ -32,7 +32,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal(v, UInt(0))
+      v := eq(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir
index a659aa07..a5278efd 100644
--- a/test/passes/split-exp/gcd.fir
+++ b/test/passes/split-exp/gcd.fir
@@ -30,7 +30,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal-uu(v, UInt(0))
+      v := eq-uu(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)
diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir
index 7a3179bf..ea316bed 100644
--- a/test/passes/to-flo/gcd.fir
+++ b/test/passes/to-flo/gcd.fir
@@ -30,7 +30,7 @@ circuit top :
       when e :
          x := a
          y := b
-      v := equal-uu(v, UInt(0))
+      v := eq-uu(v, UInt(0))
       z := x
    module top :
       input a : UInt(16)