Updated parser to correctly read empty statements

16 files changed, 287 insertions, 140 deletions

diff --git a/notes/frontend-notes.04.16.15.txt b/notes/frontend-notes.04.16.15.txt
new file mode 100644
index 00000000..14634e5e
--- /dev/null
+++ b/notes/frontend-notes.04.16.15.txt
@@ -0,0 +1,13 @@
+======= Fixes to Jonathan's Front-end ======
+Remove type from node emission
+
+Currently, these are not equivalent because we will fail a type check:
+output in { input x : UInt, input y : UInt}
+=>
+input in {x : UInt, y : UInt}
+
+Switch "input" -> "flip" and "output" to "" within a bundle
+Switch "add-mod" -> "add-wrap"
+Switch "multiplex" -> "mux"
+Switch "greater" -> "gt"
+
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index d6d33467..1ba52b03 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -75,6 +75,8 @@ defsyntax firrtl :
          Begin(body)
       comm = (?x:#exp := ?y:#exp) :
          Connect(x, y)
+      comm = (?c:skip) :
+         EmptyStmt()
       comm = (?c:#comm/when) :
          c
          
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index ae8fdbe9..310c7227 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -119,6 +119,7 @@ defmethod print (o:OutputStream, op:PrimOp) :
       CONVERT-OP : "convert"
       CONVERT-U-OP : "convert-u"
       CONVERT-S-OP : "convert-s"
+      BIT-NOT-OP : "bit-not"
       BIT-AND-OP : "bit-and"
       BIT-OR-OP : "bit-or"
       BIT-XOR-OP : "bit-xor"
@@ -169,7 +170,7 @@ defmethod print (o:OutputStream, c:Stmt) :
       (c:Connect) :
          print-all(o, [loc(c) " := " exp(c)])
       (c:EmptyStmt) :
-         print(o, "$empty$")
+         print(o, "skip")
    print-debug(o,c)
 
 defmethod print (o:OutputStream, t:Type) :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index aa940ceb..b7cce362 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -384,7 +384,7 @@ defn make-explicit-reset (c:Circuit) :
 ; Type errors are not checked in this pass, as this is
 ;   postponed for a later/earlier pass.
 
-defn get-primop-rettype (e:DoPrim) -> Type :
+defn lower-primop (e:DoPrim) -> DoPrim :
    defn u () : UIntType(UnknownWidth())
    defn s () : SIntType(UnknownWidth())
    defn u-and (op1:Expression,op2:Expression) : 
@@ -402,102 +402,211 @@ defn get-primop-rettype (e:DoPrim) -> Type :
 
    ;println-all(["Inferencing primop type: " e])
    switch {op(e) == _} :
-      ADD-OP : u-and(args(e)[0],args(e)[1])
-      ADD-UU-OP : u()
-      ADD-US-OP : s()
-      ADD-SU-OP : s()
-      ADD-SS-OP : s()
-      SUB-OP : s()
-      SUB-UU-OP : s()
-      SUB-US-OP : s()
-      SUB-SU-OP : s()
-      SUB-SS-OP : s()
-      MUL-OP : u-and(args(e)[0],args(e)[1])
-      MUL-UU-OP : u()
-      MUL-US-OP : s()
-      MUL-SU-OP : s()
-      MUL-SS-OP : s()
-      DIV-OP : u-and(args(e)[0],args(e)[1])
-      DIV-UU-OP : u()
-      DIV-US-OP : s()
-      DIV-SU-OP : s()
-      DIV-SS-OP : s()
-      MOD-OP : of-type(args(e)[0])
-      MOD-UU-OP : u()
-      MOD-US-OP : u()
-      MOD-SU-OP : s()
-      MOD-SS-OP : s()
-      QUO-OP : u-and(args(e)[0],args(e)[1])
-      QUO-UU-OP : u()
-      QUO-US-OP : s()
-      QUO-SU-OP : s()
-      QUO-SS-OP : s()
-      REM-OP : of-type(args(e)[1])
-      REM-UU-OP : u()
-      REM-US-OP : s()
-      REM-SU-OP : u()
-      REM-SS-OP : s()
-      ADD-WRAP-OP : u-and(args(e)[0],args(e)[1])
-      ADD-WRAP-UU-OP : u()
-      ADD-WRAP-US-OP : s()
-      ADD-WRAP-SU-OP : s()
-      ADD-WRAP-SS-OP : s()
-      SUB-WRAP-OP : u-and(args(e)[0],args(e)[1])
-      SUB-WRAP-UU-OP : u()
-      SUB-WRAP-US-OP : s()
-      SUB-WRAP-SU-OP : s()
-      SUB-WRAP-SS-OP : s()
-      LESS-OP : u()
-      LESS-UU-OP : u()
-      LESS-US-OP : u()
-      LESS-SU-OP : u()
-      LESS-SS-OP : u()
-      LESS-EQ-OP : u()
-      LESS-EQ-UU-OP : u()
-      LESS-EQ-US-OP : u()
-      LESS-EQ-SU-OP : u()
-      LESS-EQ-SS-OP : u()
-      GREATER-OP : u()
-      GREATER-UU-OP : u()
-      GREATER-US-OP : u()
-      GREATER-SU-OP : u()
-      GREATER-SS-OP : u()
-      GREATER-EQ-OP : u()
-      GREATER-EQ-UU-OP : u()
-      GREATER-EQ-US-OP : u()
-      GREATER-EQ-SU-OP : u()
-      GREATER-EQ-SS-OP : u()
-      EQUAL-OP : u()
-      EQUAL-UU-OP : u()
-      EQUAL-SS-OP : u()
-      MUX-OP : of-type(args(e)[0])
-      MUX-UU-OP : u()
-      MUX-SS-OP : s()
-      PAD-OP : of-type(args(e)[0])
-      PAD-U-OP : u()
-      PAD-S-OP : s()
-      AS-UINT-OP : u()
-      AS-UINT-U-OP : u()
-      AS-UINT-S-OP : u()
-      AS-SINT-OP : s()
-      AS-SINT-U-OP : s()
-      AS-SINT-S-OP : s()
-      SHIFT-LEFT-OP : of-type(args(e)[0])
-      SHIFT-LEFT-U-OP : u()
-      SHIFT-LEFT-S-OP : s()
-      SHIFT-RIGHT-OP : of-type(args(e)[0])
-      SHIFT-RIGHT-U-OP : u()
-      SHIFT-RIGHT-S-OP : s()
-      CONVERT-OP : s()
-      CONVERT-U-OP : s()
-      CONVERT-S-OP : s()
-      BIT-NOT-OP : u()
-      BIT-AND-OP : u()
-      BIT-OR-OP : u()
-      BIT-XOR-OP : u()
-      CONCAT-OP : u()
-      BIT-SELECT-OP : u()
-      BITS-SELECT-OP : u()
+      ADD-OP           : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : ADD-UU-OP
+               (t1:UIntType, t2:SIntType) : ADD-US-OP
+               (t1:SIntType, t2:UIntType) : ADD-SU-OP
+               (t1:SIntType, t2:SIntType) : ADD-SS-OP
+      ADD-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      ADD-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      ADD-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      ADD-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      SUB-UU-OP        : 
+         DoPrim{_,args(e),consts(e),s()} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : SUB-UU-OP
+               (t1:UIntType, t2:SIntType) : SUB-US-OP
+               (t1:SIntType, t2:UIntType) : SUB-SU-OP
+               (t1:SIntType, t2:SIntType) : SUB-SS-OP
+      SUB-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      SUB-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      SUB-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      MUL-OP           : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : MUL-UU-OP
+               (t1:UIntType, t2:SIntType) : MUL-US-OP
+               (t1:SIntType, t2:UIntType) : MUL-SU-OP
+               (t1:SIntType, t2:SIntType) : MUL-SS-OP
+      MUL-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      MUL-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      MUL-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      MUL-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      DIV-OP           : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : DIV-UU-OP
+               (t1:UIntType, t2:SIntType) : DIV-US-OP
+               (t1:SIntType, t2:UIntType) : DIV-SU-OP
+               (t1:SIntType, t2:SIntType) : DIV-SS-OP
+      DIV-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      DIV-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      DIV-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      DIV-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      MOD-OP           : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : MOD-UU-OP
+               (t1:UIntType, t2:SIntType) : MOD-US-OP
+               (t1:SIntType, t2:UIntType) : MOD-SU-OP
+               (t1:SIntType, t2:SIntType) : MOD-SS-OP
+      MOD-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      MOD-US-OP        : DoPrim(op(e),args(e),consts(e),u())
+      MOD-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      MOD-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      QUO-OP           : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : QUO-UU-OP
+               (t1:UIntType, t2:SIntType) : QUO-US-OP
+               (t1:SIntType, t2:UIntType) : QUO-SU-OP
+               (t1:SIntType, t2:SIntType) : QUO-SS-OP
+      QUO-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      QUO-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      QUO-SU-OP        : DoPrim(op(e),args(e),consts(e),s())
+      QUO-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      REM-OP           : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : REM-UU-OP
+               (t1:UIntType, t2:SIntType) : REM-US-OP
+               (t1:SIntType, t2:UIntType) : REM-SU-OP
+               (t1:SIntType, t2:SIntType) : REM-SS-OP
+      REM-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      REM-US-OP        : DoPrim(op(e),args(e),consts(e),s())
+      REM-SU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      REM-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      ADD-WRAP-OP      : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : ADD-WRAP-UU-OP
+               (t1:UIntType, t2:SIntType) : ADD-WRAP-US-OP
+               (t1:SIntType, t2:UIntType) : ADD-WRAP-SU-OP
+               (t1:SIntType, t2:SIntType) : ADD-WRAP-SS-OP
+      ADD-WRAP-UU-OP   : DoPrim(op(e),args(e),consts(e),u())
+      ADD-WRAP-US-OP   : DoPrim(op(e),args(e),consts(e),s())
+      ADD-WRAP-SU-OP   : DoPrim(op(e),args(e),consts(e),s())
+      ADD-WRAP-SS-OP   : DoPrim(op(e),args(e),consts(e),s())
+      SUB-WRAP-OP      : 
+         DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : SUB-WRAP-UU-OP
+               (t1:UIntType, t2:SIntType) : SUB-WRAP-US-OP
+               (t1:SIntType, t2:UIntType) : SUB-WRAP-SU-OP
+               (t1:SIntType, t2:SIntType) : SUB-WRAP-SS-OP
+      SUB-WRAP-UU-OP   : DoPrim(op(e),args(e),consts(e),u())
+      SUB-WRAP-US-OP   : DoPrim(op(e),args(e),consts(e),s())
+      SUB-WRAP-SU-OP   : DoPrim(op(e),args(e),consts(e),s())
+      SUB-WRAP-SS-OP   : DoPrim(op(e),args(e),consts(e),s())
+      LESS-OP          : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : LESS-UU-OP
+               (t1:UIntType, t2:SIntType) : LESS-US-OP
+               (t1:SIntType, t2:UIntType) : LESS-SU-OP
+               (t1:SIntType, t2:SIntType) : LESS-SS-OP
+      LESS-UU-OP       : DoPrim(op(e),args(e),consts(e),u())
+      LESS-US-OP       : DoPrim(op(e),args(e),consts(e),u())
+      LESS-SU-OP       : DoPrim(op(e),args(e),consts(e),u())
+      LESS-SS-OP       : DoPrim(op(e),args(e),consts(e),u())
+      LESS-EQ-OP       : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : LESS-EQ-UU-OP
+               (t1:UIntType, t2:SIntType) : LESS-EQ-US-OP
+               (t1:SIntType, t2:UIntType) : LESS-EQ-SU-OP
+               (t1:SIntType, t2:SIntType) : LESS-EQ-SS-OP
+      LESS-EQ-UU-OP    : DoPrim(op(e),args(e),consts(e),u())
+      LESS-EQ-US-OP    : DoPrim(op(e),args(e),consts(e),u())
+      LESS-EQ-SU-OP    : DoPrim(op(e),args(e),consts(e),u())
+      LESS-EQ-SS-OP    : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-OP       : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : GREATER-UU-OP
+               (t1:UIntType, t2:SIntType) : GREATER-US-OP
+               (t1:SIntType, t2:UIntType) : GREATER-SU-OP
+               (t1:SIntType, t2:SIntType) : GREATER-SS-OP
+      GREATER-UU-OP    : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-US-OP    : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-SU-OP    : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-SS-OP    : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-EQ-OP    : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : GREATER-EQ-UU-OP
+               (t1:UIntType, t2:SIntType) : GREATER-EQ-US-OP
+               (t1:SIntType, t2:UIntType) : GREATER-EQ-SU-OP
+               (t1:SIntType, t2:SIntType) : GREATER-EQ-SS-OP
+      GREATER-EQ-UU-OP : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-EQ-US-OP : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-EQ-SU-OP : DoPrim(op(e),args(e),consts(e),u())
+      GREATER-EQ-SS-OP : DoPrim(op(e),args(e),consts(e),u())
+      EQUAL-OP         : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : EQUAL-UU-OP
+               (t1:SIntType, t2:SIntType) : EQUAL-SS-OP
+      EQUAL-UU-OP      : DoPrim(op(e),args(e),consts(e),u())
+      EQUAL-SS-OP      : DoPrim(op(e),args(e),consts(e),u())
+      MUX-OP           : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
+            match(type(args(e)[0]),type(args(e)[0])) :
+               (t1:UIntType, t2:UIntType) : MUX-UU-OP
+               (t1:SIntType, t2:SIntType) : MUX-SS-OP
+      MUX-UU-OP        : DoPrim(op(e),args(e),consts(e),u())
+      MUX-SS-OP        : DoPrim(op(e),args(e),consts(e),s())
+      PAD-OP           : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : PAD-U-OP
+               (t1:SIntType) : PAD-S-OP
+      PAD-U-OP         : DoPrim(op(e),args(e),consts(e),u())
+      PAD-S-OP         : DoPrim(op(e),args(e),consts(e),s())
+      AS-UINT-OP       : 
+         DoPrim{_,args(e),consts(e),u()} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : AS-UINT-U-OP
+               (t1:SIntType) : AS-UINT-S-OP
+      AS-UINT-U-OP     : DoPrim(op(e),args(e),consts(e),u())
+      AS-UINT-S-OP     : DoPrim(op(e),args(e),consts(e),u())
+      AS-SINT-OP       : 
+         DoPrim{_,args(e),consts(e),s()} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : AS-SINT-U-OP
+               (t1:SIntType) : AS-SINT-S-OP
+      AS-SINT-U-OP     : DoPrim(op(e),args(e),consts(e),s())
+      AS-SINT-S-OP     : DoPrim(op(e),args(e),consts(e),s())
+      SHIFT-LEFT-OP    : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : SHIFT-LEFT-U-OP
+               (t1:SIntType) : SHIFT-LEFT-S-OP
+      SHIFT-LEFT-U-OP  : DoPrim(op(e),args(e),consts(e),u())
+      SHIFT-LEFT-S-OP  : DoPrim(op(e),args(e),consts(e),s())
+      SHIFT-RIGHT-OP   : 
+         DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : SHIFT-RIGHT-U-OP
+               (t1:SIntType) : SHIFT-RIGHT-S-OP
+      SHIFT-RIGHT-U-OP : DoPrim(op(e),args(e),consts(e),u())
+      SHIFT-RIGHT-S-OP : DoPrim(op(e),args(e),consts(e),s())
+      CONVERT-OP       : 
+         DoPrim{_,args(e),consts(e),s()} $
+            match(type(args(e)[0])) :
+               (t1:UIntType) : CONVERT-U-OP
+               (t1:SIntType) : CONVERT-S-OP
+      CONVERT-U-OP     : DoPrim(op(e),args(e),consts(e),s())
+      CONVERT-S-OP     : DoPrim(op(e),args(e),consts(e),s())
+      BIT-NOT-OP       : DoPrim(op(e),args(e),consts(e),u())
+      BIT-AND-OP       : DoPrim(op(e),args(e),consts(e),u())
+      BIT-OR-OP        : DoPrim(op(e),args(e),consts(e),u())
+      BIT-XOR-OP       : DoPrim(op(e),args(e),consts(e),u())
+      CONCAT-OP        : DoPrim(op(e),args(e),consts(e),u())
+      BIT-SELECT-OP    : DoPrim(op(e),args(e),consts(e),u())
+      BITS-SELECT-OP   : DoPrim(op(e),args(e),consts(e),u())
 
 defn type (m:Module) -> Type : 
    BundleType(for p in ports(m) map : to-field(p))
@@ -530,7 +639,8 @@ defn infer-exp-types (e:Expression, l:List<KeyValue<Symbol,Type>>) -> Expression
       (e:WSubfield) : WSubfield(exp(e),name(e), bundle-field-type(type(exp(e)),name(e)),gender(e))
       (e:WRegInit) : WRegInit(reg(e),name(e),get-type(name(reg(e) as WRef),l),gender(e))
       (e:WIndex) : WIndex(exp(e),value(e), get-vector-subtype(type(exp(e))),gender(e))
-      (e:DoPrim) : DoPrim(op(e),args(e),consts(e),get-primop-rettype(e))
+      (e:DoPrim) : lower-primop(e)
+         ;DoPrim(op(e),args(e),consts(e),get-primop-rettype(e))
       (e:ReadPort) : ReadPort(mem(e),index(e),get-vector-subtype(type(mem(e))),enable(e))
       (e:WritePort) : WritePort(mem(e),index(e),get-vector-subtype(type(mem(e))),enable(e))
       (e:UIntValue|SIntValue) : e
@@ -1647,7 +1757,7 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
       defn wmc (l:List<Expression>,c:List<Int>) :
          add-c(MinusWidth(width!(l[0]),IntWidth(c[0])))
       defn maxw (l:List<Expression>) : 
-         add-c(MaxWidth(list(width!(l[0]),width!(l[1]))))
+         add-c(MaxWidth(map(width!,l)))
       defn cons (ls:List<Expression>) : 
          val l = width!(ls[0])
          val r = width!(ls[1])
diff --git a/test/chisel3/BitsOps.fir b/test/chisel3/BitsOps.fir
index 5fa56b60..7e6c260d 100644
--- a/test/chisel3/BitsOps.fir
+++ b/test/chisel3/BitsOps.fir
@@ -1,3 +1,5 @@
+;RUN: firrtl %s abcefghipjklmno cw | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit BitsOps : 
   module BitsOps : 
     input b : UInt(16)
@@ -7,11 +9,12 @@ circuit BitsOps :
     output orout : UInt(16)
     output xorout : UInt(16)
     
-    node T_13 : UInt = bit-not(a)
+    node T_13 = bit-not(a)
     notout := T_13
-    node T_14 : UInt = bit-and(a, b)
+    node T_14 = bit-and(a, b)
     andout := T_14
-    node T_15 : UInt = bit-or(a, b)
+    node T_15 = bit-or(a, b)
     orout := T_15
-    node T_16 : UInt = bit-xor(a, b)
-    xorout := T_16
\ No newline at end of file
+    node T_16 = bit-xor(a, b)
+    xorout := T_16
+;CHECK: Finished To Flo
diff --git a/test/chisel3/BundleWire.fir b/test/chisel3/BundleWire.fir
index 72d3061e..86ffa4e8 100644
--- a/test/chisel3/BundleWire.fir
+++ b/test/chisel3/BundleWire.fir
@@ -1,9 +1,11 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit BundleWire : 
   module BundleWire : 
-    output in : {input y : UInt(32), input x : UInt(32)}
-    output outs : {output y : UInt(32), output x : UInt(32)}[4]
+    output in : {flip y : UInt(32), flip x : UInt(32)}
+    output outs : {y : UInt(32), x : UInt(32)}[4]
     
-    wire coords : {output y : UInt(32), output x : UInt(32)}[4]
+    wire coords : {y : UInt(32), x : UInt(32)}[4]
     coords.0 := in
     outs.0 := coords.0
     coords.1 := in
@@ -11,4 +13,5 @@ circuit BundleWire :
     coords.2 := in
     outs.2 := coords.2
     coords.3 := in
-    outs.3 := coords.3
\ No newline at end of file
+    outs.3 := coords.3
+;CHECK: Finished To Flo
diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir
index 2cf52370..14cb063c 100644
--- a/test/chisel3/ComplexAssign.fir
+++ b/test/chisel3/ComplexAssign.fir
@@ -1,15 +1,18 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit ComplexAssign : 
   module ComplexAssign : 
-    input in : {output re : UInt(10), output im : UInt(10)}
-    output out : {output re : UInt(10), output im : UInt(10)}
+    input in : {re : UInt(10), im : UInt(10)}
+    output out : {re : UInt(10), im : UInt(10)}
     input e : UInt(1)
     when e : 
-      wire T_19 : {output re : UInt(10), output im : UInt(10)}
+      wire T_19 : {re : UInt(10), im : UInt(10)}
       T_19 := in
       out.re := T_19.re
       out.im := T_19.im
      else : 
-      node T_20 : UInt(1) = UInt(0, 1)
+      node T_20 = UInt(0, 1)
       out.re := T_20
-      node T_21 : UInt(1) = UInt(0, 1)
-      out.im := T_21
\ No newline at end of file
+      node T_21 = UInt(0, 1)
+      out.im := T_21
+;CHECK: Finished To Flo
diff --git a/test/chisel3/Counter.fir b/test/chisel3/Counter.fir
index 8bab249c..55091d7f 100644
--- a/test/chisel3/Counter.fir
+++ b/test/chisel3/Counter.fir
@@ -1,17 +1,20 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit Counter : 
   module Counter : 
     input inc : UInt(1)
     output tot : UInt(8)
     input amt : UInt(4)
     
-    node T_13 : UInt(8) = UInt(255, 8)
-    node T_14 : UInt(8) = UInt(0, 8)
+    node T_13 = UInt(255, 8)
+    node T_14 = UInt(0, 8)
     reg T_15 : UInt(8)
     T_15.init := T_14
     when inc : 
-      node T_16 : UInt = add-mod(T_15, amt)
-      node T_17 : UInt(1) = greater(T_16, T_13)
-      node T_18 : UInt(1) = UInt(0, 1)
-      node T_19 : UInt(1) = multiplex(T_17, T_18, T_16)
+      node T_16 = add-wrap(T_15, amt)
+      node T_17 = gt(T_16, T_13)
+      node T_18 = UInt(0, 1)
+      node T_19 = mux(T_17, T_18, T_16)
       T_15 := T_19
-    tot := T_15
\ No newline at end of file
+    tot := T_15
+;CHECK: Finished To Flo
diff --git a/test/chisel3/DirChange.fir b/test/chisel3/DirChange.fir
index c948dc85..4c26650f 100644
--- a/test/chisel3/DirChange.fir
+++ b/test/chisel3/DirChange.fir
@@ -1,7 +1,10 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit DirChange : 
   module DirChange : 
     input test1 : UInt(5)
     output test2 : UInt(5)
     input test3 : UInt(2)[10]
-    output test4 : {output test41 : UInt(5), output test42 : UInt(5)}
-    skip
\ No newline at end of file
+    output test4 : {test41 : UInt(5), test42 : UInt(5)}
+    skip
+;CHECK: Finished To Flo
diff --git a/test/chisel3/EnableShiftRegister.fir b/test/chisel3/EnableShiftRegister.fir
index aa7d36ae..732e1dbc 100644
--- a/test/chisel3/EnableShiftRegister.fir
+++ b/test/chisel3/EnableShiftRegister.fir
@@ -1,19 +1,21 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit EnableShiftRegister : 
   module EnableShiftRegister : 
     input in : UInt(4)
     output out : UInt(4)
     input shift : UInt(1)
     
-    node T_14 : UInt(4) = UInt(0, 4)
+    node T_14 = UInt(0, 4)
     reg r0 : UInt(4)
     r0.init := T_14
-    node T_15 : UInt(4) = UInt(0, 4)
+    node T_15 = UInt(0, 4)
     reg r1 : UInt(4)
     r1.init := T_15
-    node T_16 : UInt(4) = UInt(0, 4)
+    node T_16 = UInt(0, 4)
     reg r2 : UInt(4)
     r2.init := T_16
-    node T_17 : UInt(4) = UInt(0, 4)
+    node T_17 = UInt(0, 4)
     reg r3 : UInt(4)
     r3.init := T_17
     when shift : 
@@ -21,4 +23,5 @@ circuit EnableShiftRegister :
       r1 := r0
       r2 := r1
       r3 := r2
-    out := r3
\ No newline at end of file
+    out := r3
+;CHECK: Finished To Flo
diff --git a/test/chisel3/GCD.fir b/test/chisel3/GCD.fir
index 5b103a6b..35da1802 100644
--- a/test/chisel3/GCD.fir
+++ b/test/chisel3/GCD.fir
@@ -1,3 +1,5 @@
+;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
+;CHECK: To Flo
 circuit GCD : 
   module GCD : 
     input b : UInt(16)
@@ -8,17 +10,18 @@ circuit GCD :
     
     reg x : UInt(16)
     reg y : UInt(16)
-    node T_17 : UInt(1) = greater(x, y)
+    node T_17 = gt(x, y)
     when T_17 : 
-      node T_18 : UInt = sub-mod(x, y)
+      node T_18 = sub-wrap(x, y)
       x := T_18
      else : 
-      node T_19 : UInt = sub-mod(y, x)
+      node T_19 = sub-wrap(y, x)
       y := T_19
     when e : 
       x := a
       y := b
     z := x
-    node T_20 : UInt(1) = UInt(0, 1)
-    node T_21 : UInt(1) = equal(y, T_20)
-    v := T_21
\ No newline at end of file
+    node T_20 = UInt(0, 1)
+    node T_21 = equal(y, T_20)
+    v := T_21
+;CHECK: Finished To Flo
diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir
index 7e661548..7d1d6073 100644
--- a/test/chisel3/LFSR16.fir
+++ b/test/chisel3/LFSR16.fir
@@ -17,4 +17,4 @@ circuit LFSR16 :
       node T_24 : UInt = bits(res, 15, 1)
       node T_25 : UInt(1) = concat(T_23, T_24)
       res := T_25
-    out := res
\ No newline at end of file
+    out := res
diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir
index f7a0fb84..78e804d1 100644
--- a/test/chisel3/MemorySearch.fir
+++ b/test/chisel3/MemorySearch.fir
@@ -40,4 +40,4 @@ circuit MemorySearch :
         node T_52 : UInt(3) = add(index, T_51)
         index := T_52
     done := done
-    address := index
\ No newline at end of file
+    address := index
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index 1372d1f6..e4c526ec 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -22,4 +22,4 @@ circuit ModuleVec :
     pluses.0.in := ins.0
     outs.0 := pluses.0.out
     pluses.1.in := ins.1
-    outs.1 := pluses.1.out
\ No newline at end of file
+    outs.1 := pluses.1.out
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index f8ba0b78..e41537e3 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -41,4 +41,4 @@ circuit Mul :
     node T_61 : UInt(2) = shift-left(x, T_60)
     node T_62 : UInt(2) = bit-or(T_61, y)
     accessor T_63 = tbl[T_62]
-    z := T_63
\ No newline at end of file
+    z := T_63
diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir
index e3a67a6e..0b808cb5 100644
--- a/test/chisel3/Outer.fir
+++ b/test/chisel3/Outer.fir
@@ -14,4 +14,4 @@ circuit Outer :
     T_17.in := in
     node T_18 : UInt(2) = UInt(2, 2)
     node T_19 : UInt(8) = times(T_17.out, T_18)
-    out := T_19
\ No newline at end of file
+    out := T_19