From 01fa067fe52081463222110b957053734e357f79 Mon Sep 17 00:00:00 2001 From: azidar Date: Fri, 17 Apr 2015 10:59:32 -0700 Subject: Fixed bug in primop lowering during type inference. Added reduce instructions and renamed concat -> cat, equal -> eq, and added neq and neg --- test/passes/expand-connect-indexed/bundle-vecs.fir | 4 +- test/passes/infer-types/gcd.fir | 8 +-- test/passes/infer-types/primops.fir | 61 +++++++++++++--------- test/passes/infer-widths/gcd.fir | 2 +- test/passes/inline/gcd.fir | 2 +- test/passes/jacktest/risc.fir | 10 ++-- test/passes/resolve-genders/gcd.fir | 6 +-- test/passes/resolve-kinds/gcd.fir | 2 +- test/passes/split-exp/gcd.fir | 2 +- test/passes/to-flo/gcd.fir | 2 +- 10 files changed, 56 insertions(+), 43 deletions(-) (limited to 'test') diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index f3754a32..e00dd9c2 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -16,10 +16,10 @@ circuit top : ; CHECK: wire b$x : UInt(32) ; CHECK: wire b$y : UInt(32) ; CHECK: b$x := a$0$x - ; CHECK: when equal-uu(i, UInt(1)) : + ; CHECK: when eq-uu(i, UInt(1)) : ; CHECK: b$x := a$1$x ; CHECK: a$0$y := b$y - ; CHECK: when equal-uu(i, UInt(1)) : + ; CHECK: when eq-uu(i, UInt(1)) : ; CHECK: a$1$y := b$y j := b diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index ea134c2f..aa43644c 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -7,7 +7,7 @@ circuit top : input y : UInt output z : UInt z := sub-wrap(x, y) - ;CHECK: z@ := sub-wrap(x@, y@)@ + ;CHECK: z@ := sub-wrap-uu(x@, y@)@ module gcd : input a : UInt(16) input b : UInt(16) @@ -20,7 +20,7 @@ circuit top : x.init := UInt(0) y.init := UInt(42) when gt(x, y) : - ;CHECK: when gt(x@, y@)@ : + ;CHECK: when gt-uu(x@, y@)@ : inst s of subtracter ;CHECK: inst s of subtracter@, y : UInt@, flip z : UInt@, reset : UInt(1)@}> s.x := x @@ -38,8 +38,8 @@ circuit top : when e : x := a y := b - v := equal(v, UInt(0)) - ;CHECK: v@ := equal(v@, UInt(0))@ + v := eq(v, UInt(0)) + ;CHECK: v@ := eq-uu(v@, UInt(0))@ z := x module top : input a : UInt(16) diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 7e7342ae..2c37f361 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -9,120 +9,133 @@ circuit top : wire d : SInt(8) wire e : UInt(1) - node vadd = add(a, c) ;CHECK: node vadd = add(a@, c@)@ + node vadd = add(a, c) ;CHECK: node vadd = add-us(a@, c@)@ node wadd-uu = add-uu(a, b) ;CHECK: node wadd-uu = add-uu(a@, b@)@ node xadd-us = add-us(a, d) ;CHECK: node xadd-us = add-us(a@, d@)@ node yadd-su = add-su(c, b) ;CHECK: node yadd-su = add-su(c@, b@)@ node zadd-ss = add-ss(c, d) ;CHECK: node zadd-ss = add-ss(c@, d@)@ - node vsub = sub(a, c) ;CHECK: node vsub = sub(a@, c@)@ + node vsub = sub(a, c) ;CHECK: node vsub = sub-us(a@, c@)@ node wsub-uu = sub-uu(a, b) ;CHECK: node wsub-uu = sub-uu(a@, b@)@ node xsub-us = sub-us(a, d) ;CHECK: node xsub-us = sub-us(a@, d@)@ node ysub-su = sub-su(c, b) ;CHECK: node ysub-su = sub-su(c@, b@)@ node zsub-ss = sub-ss(c, d) ;CHECK: node zsub-ss = sub-ss(c@, d@)@ - node vmul = mul(a, c) ;CHECK: node vmul = mul(a@, c@)@ + node vmul = mul(a, c) ;CHECK: node vmul = mul-us(a@, c@)@ node wmul-uu = mul-uu(a, b) ;CHECK: node wmul-uu = mul-uu(a@, b@)@ node xmul-us = mul-us(a, d) ;CHECK: node xmul-us = mul-us(a@, d@)@ node ymul-su = mul-su(c, b) ;CHECK: node ymul-su = mul-su(c@, b@)@ node zmul-ss = mul-ss(c, d) ;CHECK: node zmul-ss = mul-ss(c@, d@)@ - node vdiv = div(a, c) ;CHECK: node vdiv = div(a@, c@)@ + node vdiv = div(a, c) ;CHECK: node vdiv = div-us(a@, c@)@ node wdiv-uu = div-uu(a, b) ;CHECK: node wdiv-uu = div-uu(a@, b@)@ node xdiv-us = div-us(a, d) ;CHECK: node xdiv-us = div-us(a@, d@)@ node ydiv-su = div-su(c, b) ;CHECK: node ydiv-su = div-su(c@, b@)@ node zdiv-ss = div-ss(c, d) ;CHECK: node zdiv-ss = div-ss(c@, d@)@ - node vmod = mod(a, c) ;CHECK: node vmod = mod(a@, c@)@ + node vmod = mod(a, c) ;CHECK: node vmod = mod-us(a@, c@)@ node wmod-uu = mod-uu(a, b) ;CHECK: node wmod-uu = mod-uu(a@, b@)@ node xmod-us = mod-us(a, d) ;CHECK: node xmod-us = mod-us(a@, d@)@ node ymod-su = mod-su(c, b) ;CHECK: node ymod-su = mod-su(c@, b@)@ node zmod-ss = mod-ss(c, d) ;CHECK: node zmod-ss = mod-ss(c@, d@)@ - node vquo = quo(a, c) ;CHECK: node vquo = quo(a@, c@)@ + node vquo = quo(a, c) ;CHECK: node vquo = quo-us(a@, c@)@ node wquo-uu = quo-uu(a, b) ;CHECK: node wquo-uu = quo-uu(a@, b@)@ node xquo-us = quo-us(a, d) ;CHECK: node xquo-us = quo-us(a@, d@)@ node yquo-su = quo-su(c, b) ;CHECK: node yquo-su = quo-su(c@, b@)@ node zquo-ss = quo-ss(c, d) ;CHECK: node zquo-ss = quo-ss(c@, d@)@ - node vrem = rem(a, c) ;CHECK: node vrem = rem(a@, c@)@ + node vrem = rem(a, c) ;CHECK: node vrem = rem-us(a@, c@)@ node wrem-uu = rem-uu(a, b) ;CHECK: node wrem-uu = rem-uu(a@, b@)@ node xrem-us = rem-us(a, d) ;CHECK: node xrem-us = rem-us(a@, d@)@ node yrem-su = rem-su(c, b) ;CHECK: node yrem-su = rem-su(c@, b@)@ node zrem-ss = rem-ss(c, d) ;CHECK: node zrem-ss = rem-ss(c@, d@)@ - node vadd-wrap = add-wrap(a, c) ;CHECK: node vadd-wrap = add-wrap(a@, c@)@ + node vadd-wrap = add-wrap(a, c) ;CHECK: node vadd-wrap = add-wrap-us(a@, c@)@ node wadd-wrap-uu = add-wrap-uu(a, b) ;CHECK: node wadd-wrap-uu = add-wrap-uu(a@, b@)@ node xadd-wrap-us = add-wrap-us(a, d) ;CHECK: node xadd-wrap-us = add-wrap-us(a@, d@)@ node yadd-wrap-su = add-wrap-su(c, b) ;CHECK: node yadd-wrap-su = add-wrap-su(c@, b@)@ node zadd-wrap-ss = add-wrap-ss(c, d) ;CHECK: node zadd-wrap-ss = add-wrap-ss(c@, d@)@ - node vsub-wrap = sub-wrap(a, c) ;CHECK: node vsub-wrap = sub-wrap(a@, c@)@ + node vsub-wrap = sub-wrap(a, c) ;CHECK: node vsub-wrap = sub-wrap-us(a@, c@)@ node wsub-wrap-uu = sub-wrap-uu(a, b) ;CHECK: node wsub-wrap-uu = sub-wrap-uu(a@, b@)@ node xsub-wrap-us = sub-wrap-us(a, d) ;CHECK: node xsub-wrap-us = sub-wrap-us(a@, d@)@ node ysub-wrap-su = sub-wrap-su(c, b) ;CHECK: node ysub-wrap-su = sub-wrap-su(c@, b@)@ node zsub-wrap-ss = sub-wrap-ss(c, d) ;CHECK: node zsub-wrap-ss = sub-wrap-ss(c@, d@)@ - node vlt = lt(a, c) ;CHECK: node vlt = lt(a@, c@)@ + node vlt = lt(a, c) ;CHECK: node vlt = lt-us(a@, c@)@ node wlt-uu = lt-uu(a, b) ;CHECK: node wlt-uu = lt-uu(a@, b@)@ node xlt-us = lt-us(a, d) ;CHECK: node xlt-us = lt-us(a@, d@)@ node ylt-su = lt-su(c, b) ;CHECK: node ylt-su = lt-su(c@, b@)@ node zlt-ss = lt-ss(c, d) ;CHECK: node zlt-ss = lt-ss(c@, d@)@ - node vleq = leq(a, c) ;CHECK: node vleq = leq(a@, c@)@ + node vleq = leq(a, c) ;CHECK: node vleq = leq-us(a@, c@)@ node wleq-uu = leq-uu(a, b) ;CHECK: node wleq-uu = leq-uu(a@, b@)@ node xleq-us = leq-us(a, d) ;CHECK: node xleq-us = leq-us(a@, d@)@ node yleq-su = leq-su(c, b) ;CHECK: node yleq-su = leq-su(c@, b@)@ node zleq-ss = leq-ss(c, d) ;CHECK: node zleq-ss = leq-ss(c@, d@)@ - node vgt = gt(a, c) ;CHECK: node vgt = gt(a@, c@)@ + node vgt = gt(a, c) ;CHECK: node vgt = gt-us(a@, c@)@ node wgt-uu = gt-uu(a, b) ;CHECK: node wgt-uu = gt-uu(a@, b@)@ node xgt-us = gt-us(a, d) ;CHECK: node xgt-us = gt-us(a@, d@)@ node ygt-su = gt-su(c, b) ;CHECK: node ygt-su = gt-su(c@, b@)@ node zgt-ss = gt-ss(c, d) ;CHECK: node zgt-ss = gt-ss(c@, d@)@ - node vgeq = geq(a, c) ;CHECK: node vgeq = geq(a@, c@)@ + node vgeq = geq(a, c) ;CHECK: node vgeq = geq-us(a@, c@)@ node wgeq-uu = geq-uu(a, b) ;CHECK: node wgeq-uu = geq-uu(a@, b@)@ node xgeq-us = geq-us(a, d) ;CHECK: node xgeq-us = geq-us(a@, d@)@ node ygeq-su = geq-su(c, b) ;CHECK: node ygeq-su = geq-su(c@, b@)@ node zgeq-ss = geq-ss(c, d) ;CHECK: node zgeq-ss = geq-ss(c@, d@)@ - node vequal = equal(a, b) ;CHECK: node vequal = equal(a@, b@)@ - node wequal-uu = equal-uu(a, b) ;CHECK: node wequal-uu = equal-uu(a@, b@)@ - node zequal-ss = equal-ss(c, d) ;CHECK: node zequal-ss = equal-ss(c@, d@)@ + node vneq = neq(a, b) ;CHECK: node vneq = neq-uu(a@, b@)@ + node wneq-uu = neq-uu(a, b) ;CHECK: node wneq-uu = neq-uu(a@, b@)@ + node zneq-ss = neq-ss(c, d) ;CHECK: node zneq-ss = neq-ss(c@, d@)@ - node vmux = mux(e, a, b) ;CHECK: node vmux = mux(e@, a@, b@)@ + node veq = eq(a, b) ;CHECK: node veq = eq-uu(a@, b@)@ + node weq-uu = eq-uu(a, b) ;CHECK: node weq-uu = eq-uu(a@, b@)@ + node zeq-ss = eq-ss(c, d) ;CHECK: node zeq-ss = eq-ss(c@, d@)@ + + node vmux = mux(e, a, b) ;CHECK: node vmux = mux-uu(e@, a@, b@)@ node wmux-uu = mux-uu(e, a, b) ;CHECK: node wmux-uu = mux-uu(e@, a@, b@)@ node zmux-ss = mux-ss(e, c, d) ;CHECK: node zmux-ss = mux-ss(e@, c@, d@)@ - node vpad = pad(a, 10) ;CHECK: node vpad = pad(a@, 10)@ + node vpad = pad(a, 10) ;CHECK: node vpad = pad-u(a@, 10)@ node wpad-u = pad-u(a, 10) ;CHECK: node wpad-u = pad-u(a@, 10)@ node zpad-s = pad-s(c, 10) ;CHECK: node zpad-s = pad-s(c@, 10)@ - node vas-UInt = as-UInt(d) ;CHECK: node vas-UInt = as-UInt(d@)@ + node vas-UInt = as-UInt(d) ;CHECK: node vas-UInt = as-UInt-s(d@)@ node was-UInt-u = as-UInt-u(a) ;CHECK: node was-UInt-u = as-UInt-u(a@)@ node zas-UInt-s = as-UInt-s(c) ;CHECK: node zas-UInt-s = as-UInt-s(c@)@ - node vas-SInt = as-SInt(a) ;CHECK: node vas-SInt = as-SInt(a@)@ + node vas-SInt = as-SInt(a) ;CHECK: node vas-SInt = as-SInt-u(a@)@ node was-SInt-u = as-SInt-u(a) ;CHECK: node was-SInt-u = as-SInt-u(a@)@ node zas-SInt-s = as-SInt-s(c) ;CHECK: node zas-SInt-s = as-SInt-s(c@)@ - node vshl = shl(a, 10) ;CHECK: node vshl = shl(a@, 10)@ + node vshl = shl(a, 10) ;CHECK: node vshl = shl-u(a@, 10)@ node wshl-u = shl-u(a, 10) ;CHECK: node wshl-u = shl-u(a@, 10)@ node zshl-s = shl-s(c, 10) ;CHECK: node zshl-s = shl-s(c@, 10)@ - node vshr = shr(a, 10) ;CHECK: node vshr = shr(a@, 10)@ + node vshr = shr(a, 10) ;CHECK: node vshr = shr-u(a@, 10)@ node wshr-u = shr-u(a, 10) ;CHECK: node wshr-u = shr-u(a@, 10)@ node zshr-s = shr-s(c, 10) ;CHECK: node zshr-s = shr-s(c@, 10)@ - node vconvert = convert(a) ;CHECK: node vconvert = convert(a@)@ + node vconvert = convert(a) ;CHECK: node vconvert = convert-u(a@)@ node wconvert-u = convert-u(a) ;CHECK: node wconvert-u = convert-u(a@)@ node zconvert-s = convert-s(c) ;CHECK: node zconvert-s = convert-s(c@)@ + node vneg = neg(a) ;CHECK: node vneg = neg-u(a@)@ + node wneg-u = neg-u(a) ;CHECK: node wneg-u = neg-u(a@)@ + node zneg-s = neg-s(c) ;CHECK: node zneg-s = neg-s(c@)@ + node uand = bit-and(a, b) ;CHECK: node uand = bit-and(a@, b@)@ node vor = bit-or(a, b) ;CHECK: node vor = bit-or(a@, b@)@ node wxor = bit-xor(a, b) ;CHECK: node wxor = bit-xor(a@, b@)@ - node xconcat = concat(a, b) ;CHECK: node xconcat = concat(a@, b@)@ + node xcat = cat(a, b) ;CHECK: node xcat = cat(a@, b@)@ node ybit = bit(a, 0) ;CHECK: node ybit = bit(a@, 0)@ node zbits = bits(a, 2, 0) ;CHECK: node zbits = bits(a@, 2, 0)@ + + node uand-reduce = bit-and-reduce(a, b, a) ;CHECK: node uand-reduce = bit-and-reduce(a@, b@, a@)@ + node uor-reduce = bit-or-reduce(a, b, a) ;CHECK: node uor-reduce = bit-or-reduce(a@, b@, a@)@ + node uxor-reduce = bit-xor-reduce(a, b, a) ;CHECK: node uxor-reduce = bit-xor-reduce(a@, b@, a@)@ + ;CHECK: Finished Infer Types diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index 2adba2b8..f9f7ac5c 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := equal-uu(v, UInt(0)) + v := eq-uu(v, UInt(0)) z := x module top : input a : UInt(16) diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir index bf6f87ab..5713cd43 100644 --- a/test/passes/inline/gcd.fir +++ b/test/passes/inline/gcd.fir @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := equal-uu(v, UInt(0)) + v := eq-uu(v, UInt(0)) z := x module top : input a : UInt(16) diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir index d8197112..bf3eaf01 100644 --- a/test/passes/jacktest/risc.fir +++ b/test/passes/jacktest/risc.fir @@ -22,12 +22,12 @@ circuit Risc : node rai = bits(inst, 15, 8) node rbi = bits(inst, 7, 0) node T_52 = UInt(0, 1) - node T_53 = equal(rai, T_52) + node T_53 = eq(rai, T_52) node T_54 = UInt(0, 1) accessor T_55 = file[rai] node ra = mux(T_53, T_54, T_55) node T_56 = UInt(0, 1) - node T_57 = equal(rbi, T_56) + node T_57 = eq(rbi, T_56) node T_58 = UInt(0, 1) accessor T_59 = file[rbi] node rb = mux(T_57, T_58, T_59) @@ -45,18 +45,18 @@ circuit Risc : node T_64 = UInt(0, 1) pc := T_64 else : - node T_65 = equal(add_op, op) + node T_65 = eq(add_op, op) when T_65 : node T_66 = add-wrap(ra, rb) rc := T_66 - node T_67 = equal(imm_op, op) + node T_67 = eq(imm_op, op) when T_67 : node T_68 = shl(rai, 8) node T_69 = bit-or(T_68, rbi) rc := T_69 out := rc node T_70 = UInt(255, 8) - node T_71 = equal(rci, T_70) + node T_71 = eq(rci, T_70) when T_71 : node T_72 = UInt(1, 1) valid := T_72 diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir index 1f41cacd..2190d284 100644 --- a/test/passes/resolve-genders/gcd.fir +++ b/test/passes/resolve-genders/gcd.fir @@ -7,7 +7,7 @@ circuit top : input y : UInt output z : UInt z := sub-wrap(x, y) - ;CHECK: z@ := sub-wrap(x@, y@) + ;CHECK: z@ := sub-wrap-uu(x@, y@) module gcd : input a : UInt(16) input b : UInt(16) @@ -20,7 +20,7 @@ circuit top : x.init := UInt(0) y.init := UInt(42) when gt(x, y) : - ;CHECK: when gt(x@, y@) : + ;CHECK: when gt-uu(x@, y@) : inst s of subtracter ;CHECK: inst s of subtracter@ s.x := x @@ -37,7 +37,7 @@ circuit top : when e : x := a y := b - v := equal(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt(16) diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir index f4ad0e05..e7cd8f34 100644 --- a/test/passes/resolve-kinds/gcd.fir +++ b/test/passes/resolve-kinds/gcd.fir @@ -32,7 +32,7 @@ circuit top : when e : x := a y := b - v := equal(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt(16) diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index a659aa07..a5278efd 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := equal-uu(v, UInt(0)) + v := eq-uu(v, UInt(0)) z := x module top : input a : UInt(16) diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir index 7a3179bf..ea316bed 100644 --- a/test/passes/to-flo/gcd.fir +++ b/test/passes/to-flo/gcd.fir @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := equal-uu(v, UInt(0)) + v := eq-uu(v, UInt(0)) z := x module top : input a : UInt(16) -- cgit v1.2.3