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| author | azidar | 2015-04-16 10:29:08 -0700 |
|---|---|---|
| committer | azidar | 2015-04-16 10:29:08 -0700 |
| commit | bd9eaea8a6ba91ad77988cd82e89c058ad05ef2a (patch) | |
| tree | 6519dc1338bbeeb00099c46a3fa266866d11c0dd /test | |
| parent | f9b341d59e7597b46ac6354f97e83a5e96036c5c (diff) | |
| parent | 5d9f23db98f003b14cc4f47b7c92c414131b780f (diff) | |
Merged with new stanza
Diffstat (limited to 'test')
| -rw-r--r-- | test/passes/resolve-genders/bulk.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir index 0276715f..ab549975 100644 --- a/test/passes/resolve-genders/bulk.fir +++ b/test/passes/resolve-genders/bulk.fir @@ -3,9 +3,9 @@ ;CHECK: Resolve Genders circuit top : module source : - output bundle : { male data : UInt(16), female ready : UInt(1) } + output bundle : { data : UInt(16), flip ready : UInt(1) } module sink : - input bundle : { male data : UInt(16), female ready : UInt(1) } + input bundle : { data : UInt(16), flip ready : UInt(1) } module top : inst src of source inst snk of sink |