Finished expand accessors pass. Fixed bug in resolve-gender. Added tests, all pass. Minimal removal of letrec to get WritePort to work correctly - a more thorough removeal is still needed

4 files changed, 115 insertions, 0 deletions

diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
new file mode 100644
index 00000000..32002d47
--- /dev/null
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -0,0 +1,19 @@
+; RUN: firrtl %s abcdefg c | tee %s.out | FileCheck %s
+
+;CHECK: Expand Accessors
+circuit top :
+   module top :
+      mem m : UInt(32)[10][10][10]
+      wire i : UInt
+      accessor a = m[i] ;CHECK: a := ReadPort(m, i, UInt(1))
+      accessor b = a[i] ;CHECK: b := (a.9 a.8 a.7 a.6 a.5 a.4 a.3 a.2 a.1 a.0)[i]
+      accessor c = b[i] ;CHECK: c := (b.9 b.8 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0)[i]
+      wire j : UInt
+      j := c
+
+      accessor x = m[i] ;CHECK: WritePort(m, i, UInt(1)) := x
+      accessor y = x[i] ;CHECK: (x.9 x.8 x.7 x.6 x.5 x.4 x.3 x.2 x.1 x.0)[i] := y
+      accessor z = y[i] ;CHECK: (y.9 y.8 y.7 y.6 y.5 y.4 y.3 y.2 y.1 y.0)[i] := z
+      z := j
+
+; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir
new file mode 100644
index 00000000..4314e062
--- /dev/null
+++ b/test/passes/expand-accessors/accessor-vec.fir
@@ -0,0 +1,19 @@
+; RUN: firrtl %s abcdefg c | tee %s.out | FileCheck %s
+
+;CHECK: Expand Accessors
+circuit top :
+   module top :
+      wire m : UInt(32)[10][10][10]
+      wire i : UInt
+      accessor a = m[i] ;CHECK: a := (m.9 m.8 m.7 m.6 m.5 m.4 m.3 m.2 m.1 m.0)[i]
+      accessor b = a[i] ;CHECK: b := (a.9 a.8 a.7 a.6 a.5 a.4 a.3 a.2 a.1 a.0)[i]
+      accessor c = b[i] ;CHECK: c := (b.9 b.8 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0)[i]
+      wire j : UInt
+      j := c
+
+      accessor x = m[i] ;CHECK: (m.9 m.8 m.7 m.6 m.5 m.4 m.3 m.2 m.1 m.0)[i] := x
+      accessor y = x[i] ;CHECK: (x.9 x.8 x.7 x.6 x.5 x.4 x.3 x.2 x.1 x.0)[i] := y
+      accessor z = y[i] ;CHECK: (y.9 y.8 y.7 y.6 y.5 y.4 y.3 y.2 y.1 y.0)[i] := z
+      z := j
+
+; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/one-when.fir b/test/passes/expand-accessors/one-when.fir
new file mode 100644
index 00000000..2597c1d7
--- /dev/null
+++ b/test/passes/expand-accessors/one-when.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl %s abcdefg c | tee %s.out | FileCheck %s
+
+;CHECK: Expand Accessors
+circuit top :
+   module top :
+      mem m : UInt(1)[2]
+      wire i : UInt(1)
+      wire p : UInt(1)
+      when p :
+        accessor a = m[i] ;CHECK: a := ReadPort(m, i, bit-and(p, UInt(1)))
+        i := a
+        accessor b = m[i] ;CHECK: WritePort(m, i, bit-and(p, UInt(1))) := b
+        b := i
+      else :
+        accessor c = m[i] ;CHECK: c := ReadPort(m, i, bit-and(equal-uu(UInt(0), p), UInt(1)))
+        i := c
+        accessor d = m[i] ;CHECK: WritePort(m, i, bit-and(equal-uu(UInt(0), p), UInt(1))) := d
+        d := i
+
+; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/two-when.fir b/test/passes/expand-accessors/two-when.fir
new file mode 100644
index 00000000..87c8fc54
--- /dev/null
+++ b/test/passes/expand-accessors/two-when.fir
@@ -0,0 +1,57 @@
+; RUN: firrtl %s abcdefg c | tee %s.out | FileCheck %s
+
+;CHECK: Expand Accessors
+circuit top :
+   module top :
+      mem m : UInt(1)[2]
+      wire i : UInt(1)
+      wire p : UInt(1)
+      when p :
+        wire p2 : UInt(1)
+        when p2 :
+          accessor a = m[i] 
+          i := a
+          accessor b = m[i]
+          b := i
+            ;CHECK : wire a : UInt(1)
+            ;CHECK : a := ReadPort(m, i, bit-and(p2, bit-and(p, UInt(1))))
+            ;CHECK : i := a
+            ;CHECK : wire b : UInt(1)
+            ;CHECK : WritePort(m, i, bit-and(p2, bit-and(p, UInt(1)))) := b
+            ;CHECK : b := i
+        else :
+          accessor c = m[i] 
+          i := c
+          accessor d = m[i]
+          d := i
+            ;CHECK : wire c : UInt(1)
+            ;CHECK : c := ReadPort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(p, UInt(1))))
+            ;CHECK : i := c
+            ;CHECK : wire d : UInt(1)
+            ;CHECK : WritePort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(p, UInt(1)))) := d
+            ;CHECK : d := i
+      else :
+        when p2 :
+          accessor w = m[i] 
+          i := w
+          accessor x = m[i]
+          x := i
+            ;CHECK : wire w : UInt(1)
+            ;CHECK : w := ReadPort(m, i, bit-and(p2, bit-and(equal-uu(UInt(0), p), UInt(1))))
+            ;CHECK : i := w
+            ;CHECK : wire x : UInt(1)
+            ;CHECK : WritePort(m, i, bit-and(p2, bit-and(equal-uu(UInt(0), p), UInt(1)))) := x
+            ;CHECK : x := i
+        else :
+          accessor y = m[i] 
+          i := y
+          accessor z = m[i]
+          z := i
+            ;CHECK : wire y : UInt(1)
+            ;CHECK : y := ReadPort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(equal-uu(UInt(0), p), UInt(1))))
+            ;CHECK : i := y
+            ;CHECK : wire z : UInt(1)
+            ;CHECK : WritePort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(equal-uu(UInt(0), p), UInt(1)))) := z
+            ;CHECK : z := i
+
+; CHECK: Finished Expand Accessors