Added on-reset

8 files changed, 91 insertions, 89 deletions

diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
new file mode 100644
index 00000000..48336c93
--- /dev/null
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -0,0 +1,25 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p cd | tee %s.out | FileCheck %s
+; CHECK: Expand Whens
+circuit top :
+   module A :
+      reg r : { x : UInt, flip y : UInt}
+      wire a : UInt
+      wire b : UInt
+      wire w : { x : UInt, flip y : UInt}
+      a := UInt(1)
+      b := UInt(2)
+
+      w.x := b
+      w.y := a
+      r.x := a
+      r.y := b
+      on-reset r := w
+
+; CHECK: r$x := Register(mux-uu(reset, w$x, a), UInt(1))
+; CHECK: r$y := Register(b, UInt(1))
+; CHECK: a := UInt(1)
+; CHECK: b := UInt(2)
+; CHECK: w$x := b
+; CHECK: w$y := mux-uu(reset, r$y, a)   
+      
+; CHECK: Finished Expand Whens
diff --git a/test/passes/initialize-regs/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index 28cbc53d..8185dade 100644
--- a/test/passes/initialize-regs/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -1,5 +1,5 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijk -p c | tee %s.out | FileCheck %s
+; CHECK: Expand Whens
 circuit top :
    module A :
       wire p : UInt
@@ -10,17 +10,15 @@ circuit top :
       wire x : UInt
       wire y : UInt
       wire z : UInt
+      wire w : UInt
 
       on-reset r := w
-      when p
+      when p :
         on-reset r := x
         r := a
-      when q
+      when q :
         on-reset r := y
         r := b
       r := z
-      
-; CHECK: r := z
-; CHECK: when reset
-; CHECK:    r := q?b:(p?a:w)
-
+; CHECK: r := Register(mux-uu(reset, mux-uu(q, y, mux-uu(p, x, w)), z), UInt(1))
+; CHECK: Finished Expand Whens
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index 0e9b5fed..3cd5c542 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cTd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cd | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Widths
 circuit top :
diff --git a/test/passes/initialize-regs/bundle-init.fir b/test/passes/initialize-regs/bundle-init.fir
deleted file mode 100644
index 7e9af8df..00000000
--- a/test/passes/initialize-regs/bundle-init.fir
+++ /dev/null
@@ -1,21 +0,0 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
-circuit top :
-   module A :
-      reg r : { x : UInt, flip y : UInt}
-      wire a : UInt
-      wire b : UInt
-      wire w : { x : UInt, flip y : UInt}
-
-      r.x := a
-      r.y := b
-      on-reset r := w
-      
-; CHECK: reg r : { x, flip y}
-; CHECK: r.x := a
-; CHECK: r.y := b
-; CHECK: when reset :
-; CHECK:    r.x := w.x
-; CHECK:    w.y := r.y
-
-
diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
index 955d44f2..60b62ac7 100644
--- a/test/passes/jacktest/MemorySearch.fir
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -3,43 +3,43 @@
 
 circuit MemorySearch : 
   module MemorySearch : 
-    input target : UInt(4)
-    output address : UInt(3)
-    input en : UInt(1)
-    output done : UInt(1)
+    input target : UInt<4>
+    output address : UInt<3>
+    input en : UInt<1>
+    output done : UInt<1>
     
-    node T_35 = UInt(0, 3)
-    reg index : UInt(3)
-    index.init := T_35
-    node T_36 = UInt(0, 1)
-    node T_37 = UInt(4, 3)
-    node T_38 = UInt(15, 4)
-    node T_39 = UInt(14, 4)
-    node T_40 = UInt(2, 2)
-    node T_41 = UInt(5, 3)
-    node T_42 = UInt(13, 4)
-    wire elts : UInt(1)[7]
-    elts.0 := Pad(T_36,?)
-    elts.1 := Pad(T_37,?)
-    elts.2 := Pad(T_38,?)
-    elts.3 := Pad(T_39,?)
-    elts.4 := Pad(T_40,?)
-    elts.5 := Pad(T_41,?)
-    elts.6 := Pad(T_42,?)
+    node T_35 = UInt<3>(0)
+    reg index : UInt<3>
+    on-reset index := T_35
+    node T_36 = UInt<1>(0)
+    node T_37 = UInt<3>(4)
+    node T_38 = UInt<4>(15)
+    node T_39 = UInt<4>(14)
+    node T_40 = UInt<2>(2)
+    node T_41 = UInt<3>(5)
+    node T_42 = UInt<4>(13)
+    wire elts : UInt<1>[7]
+    elts[0] := Pad(T_36,?)
+    elts[1] := Pad(T_37,?)
+    elts[2] := Pad(T_38,?)
+    elts[3] := Pad(T_39,?)
+    elts[4] := Pad(T_40,?)
+    elts[5] := Pad(T_41,?)
+    elts[6] := Pad(T_42,?)
     accessor elt = elts[index]
     node T_43 = bit-not(en)
     node T_44 = eq(Pad(elt,?), Pad(target,?))
-    node T_45 = UInt(7, 3)
+    node T_45 = UInt<3>(7)
     node T_46 = eq(Pad(index,?), Pad(T_45,?))
     node T_47 = bit-or(T_44, T_46)
     node end = bit-and(T_43, T_47)
     when en : 
-      node T_48 = UInt(0, 1)
+      node T_48 = UInt<1>(0)
       index := Pad(T_48,?)
     else : 
       node T_49 = bit-not(end)
       when T_49 : 
-        node T_50 = UInt(1, 1)
+        node T_50 = UInt<1>(1)
         node T_51 = add-wrap(Pad(index,?), Pad(T_50,?))
         index := Pad(T_51,?)
     done := Pad(end,?)
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
index 733e2036..832bd279 100644
--- a/test/passes/jacktest/RegisterVecShift.fir
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -3,35 +3,35 @@
 
 circuit RegisterVecShift : 
   module RegisterVecShift : 
-    input load : UInt(1)
-    output out : UInt(4)
-    input shift : UInt(1)
-    input ins : UInt(4)[4]
+    input load : UInt<1>
+    output out : UInt<4>
+    input shift : UInt<1>
+    input ins : UInt<4>[4]
     
-    reg delays : UInt(4)[4]
+    reg delays : UInt<4>[4]
     when reset : 
-      node T_38 = UInt(0, 4)
-      node T_39 = UInt(0, 4)
-      node T_40 = UInt(0, 4)
-      node T_41 = UInt(0, 4)
-      wire T_42 : UInt(4)[4]
-      T_42.0 := T_38
-      T_42.1 := T_39
-      T_42.2 := T_40
-      T_42.3 := T_41
+      node T_38 = UInt<4>(0)
+      node T_39 = UInt<4>(0)
+      node T_40 = UInt<4>(0)
+      node T_41 = UInt<4>(0)
+      wire T_42 : UInt<4>[4]
+      T_42[0] := T_38
+      T_42[1] := T_39
+      T_42[2] := T_40
+      T_42[3] := T_41
       delays := T_42
-    node T_43 = UInt(5, 3)
+    node T_43 = UInt<3>(5)
     node T_44 = bit-and(Pad(T_43,?), Pad(load,?))
-    node T_45 = UInt(4, 3)
+    node T_45 = UInt<3>(4)
     node T_46 = eq(Pad(T_44,?), Pad(T_45,?))
     when T_46 : 
-      delays.0 := Pad(ins.0,?)
-      delays.1 := Pad(ins.1,?)
-      delays.2 := Pad(ins.2,?)
-      delays.3 := Pad(ins.3,?)
+      delays[0] := Pad(ins[0],?)
+      delays[1] := Pad(ins[1],?)
+      delays[2] := Pad(ins[2],?)
+      delays[3] := Pad(ins[3],?)
     else : when shift : 
-        delays.0 := Pad(ins.0,?)
-        delays.1 := Pad(delays.0,?)
-        delays.2 := Pad(delays.1,?)
-        delays.3 := Pad(delays.2,?)
-    out := Pad(delays.3,?)
+        delays[0] := Pad(ins[0],?)
+        delays[1] := Pad(delays[0],?)
+        delays[2] := Pad(delays[1],?)
+        delays[3] := Pad(delays[2],?)
+    out := Pad(delays[3],?)
diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir
index 35442ac8..b458ac4a 100644
--- a/test/passes/jacktest/Tlb.fir
+++ b/test/passes/jacktest/Tlb.fir
@@ -2,13 +2,13 @@
 ; CHECK: Done!
 circuit Tbl : 
   module Tbl : 
-    output o : UInt(16)
-    input i : UInt(16)
-    input d : UInt(16)
-    input we : UInt(1)
+    output o : UInt<16>
+    input i : UInt<16>
+    input d : UInt<16>
+    input we : UInt<1>
     
-    mem m : UInt(10)[256]
-    node T_12 = UInt(0, 1)
+    mem m : UInt<10>[256]
+    node T_12 = UInt<1>(0)
     o := Pad(T_12,?)
     when we : 
       accessor T_13 = m[i]
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index ecc427d9..918710a5 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -15,7 +15,7 @@
       ; CHECK: reg r1$y : SInt
       ; CHECK: wire q$x : UInt
       ; CHECK: wire q$y : SInt
-      ; CHECK: r1$x.init := q$x
-      ; CHECK: q$y := r1$y.init
+      ; CHECK: on-reset r1$x := q$x
+      ; CHECK: on-reset q$y := r1$y   
 
 ; CHECK: Finished Lower To Ground