Fixed bug in lowering that incorrectly determined genders when subfielded

8 files changed, 91 insertions, 78 deletions

diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index ce14c7ba..f3754a32 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -7,20 +7,20 @@ circuit top :
       wire j : UInt
 
       wire a : { x : UInt(32), flip y : UInt(32) }[2]
-      ; CHECK: wire a#0#x : UInt(32)
-      ; CHECK: wire a#0#y : UInt(32)
-      ; CHECK: wire a#1#x : UInt(32)
-      ; CHECK: wire a#1#y : UInt(32)
+      ; CHECK: wire a$0$x : UInt(32)
+      ; CHECK: wire a$0$y : UInt(32)
+      ; CHECK: wire a$1$x : UInt(32)
+      ; CHECK: wire a$1$y : UInt(32)
 
       accessor b = a[i]
-      ; CHECK: wire b#x : UInt(32)
-      ; CHECK: wire b#y : UInt(32)
-      ; CHECK: b#x := a#0#x
+      ; CHECK: wire b$x : UInt(32)
+      ; CHECK: wire b$y : UInt(32)
+      ; CHECK: b$x := a$0$x
       ; CHECK: when equal-uu(i, UInt(1)) :
-      ; CHECK:    b#x := a#1#x
-      ; CHECK: a#0#y := b#y
+      ; CHECK:    b$x := a$1$x
+      ; CHECK: a$0$y := b$y
       ; CHECK: when equal-uu(i, UInt(1)) :
-      ; CHECK:    a#1#y := b#y
+      ; CHECK:    a$1$y := b$y
       j := b
       
 ; CHECK: Finished Expand Indexed Connects
diff --git a/test/passes/jacktest/bundlewire.fir b/test/passes/jacktest/bundlewire.fir
index 0d0f0377..0356597e 100644
--- a/test/passes/jacktest/bundlewire.fir
+++ b/test/passes/jacktest/bundlewire.fir
@@ -1,10 +1,10 @@
-; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s 
+; RUN: firrtl %s abcefghipj cg | tee %s.out | FileCheck %s 
 
 ; CHECK: Expand Whens
 
 circuit BundleWire : 
   module BundleWire : 
-    output in : { y : UInt(32), x : UInt(32) }
+    input in : { y : UInt(32), x : UInt(32) }
     output outs : { y : UInt(32), x : UInt(32) }[4]
     
     wire coords : { y : UInt(32), x : UInt(32) }[4]
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index e54868bc..8c12137f 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -7,19 +7,19 @@ circuit top :
       wire j : UInt(32)
 
       wire a : UInt(32)[4]
-      ; CHECK: wire a#0 : UInt(32)
-      ; CHECK: wire a#1 : UInt(32)
-      ; CHECK: wire a#2 : UInt(32)
-      ; CHECK: wire a#3 : UInt(32)
+      ; CHECK: wire a$0 : UInt(32)
+      ; CHECK: wire a$1 : UInt(32)
+      ; CHECK: wire a$2 : UInt(32)
+      ; CHECK: wire a$3 : UInt(32)
 
       accessor b = a[i]
       ; CHECK: wire b : UInt(32)
-      ; CHECK: b := (a#0 a#1 a#2 a#3)[i]
+      ; CHECK: b := (a$0 a$1 a$2 a$3)[i]
       j := b
 
       accessor c = a[i]
       ; CHECK: wire c : UInt(32)
-      ; CHECK: (a#0 a#1 a#2 a#3)[i] := c
+      ; CHECK: (a$0 a$1 a$2 a$3)[i] := c
       c := j
       
       mem p : UInt(32)[4]
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index a4ead6ed..f1b25854 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -7,23 +7,23 @@ circuit top :
       wire j : UInt
 
       wire a : { x : UInt(32), flip y : UInt(32) }[2]
-      ; CHECK: wire a#0#x : UInt(32)
-      ; CHECK: wire a#0#y : UInt(32)
-      ; CHECK: wire a#1#x : UInt(32)
-      ; CHECK: wire a#1#y : UInt(32)
+      ; CHECK: wire a$0$x : UInt(32)
+      ; CHECK: wire a$0$y : UInt(32)
+      ; CHECK: wire a$1$x : UInt(32)
+      ; CHECK: wire a$1$y : UInt(32)
 
       accessor b = a[i]
-      ; CHECK: wire b#x : UInt(32)
-      ; CHECK: wire b#y : UInt(32)
-      ; CHECK: b#x := (a#0#x a#1#x)[i]
-      ; CHECK: (a#0#y a#1#y)[i] := b#y
+      ; CHECK: wire b$x : UInt(32)
+      ; CHECK: wire b$y : UInt(32)
+      ; CHECK: b$x := (a$0$x a$1$x)[i]
+      ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
       
       accessor c = a[i]
-      ; CHECK: wire c#x : UInt(32)
-      ; CHECK: wire c#y : UInt(32)
-      ; CHECK: (a#0#x a#1#x)[i] := c#x
-      ; CHECK: c#y := (a#0#y a#1#y)[i]
+      ; CHECK: wire c$x : UInt(32)
+      ; CHECK: wire c$y : UInt(32)
+      ; CHECK: (a$0$x a$1$x)[i] := c$x
+      ; CHECK: c$y := (a$0$y a$1$y)[i]
       c := j
 
 
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index 990b6b7f..2947eb8f 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -17,37 +17,37 @@ circuit top :
 ;CHECK: Lower To Ground
 ;CHECK: circuit top :
 ;CHECK:    module m :
-;CHECK:       input a#x : UInt
-;CHECK:       output a#y : SInt
-;CHECK:       output b#x : UInt
-;CHECK:       input b#y : SInt
+;CHECK:       input a$x : UInt
+;CHECK:       output a$y : SInt
+;CHECK:       output b$x : UInt
+;CHECK:       input b$y : SInt
 ;CHECK:       input reset : UInt(1)
 ;CHECK:    module subtracter :
-;CHECK:       input c#x#0 : UInt
-;CHECK:       input c#x#1 : UInt
-;CHECK:       input c#x#2 : UInt
-;CHECK:       input c#x#3 : UInt
-;CHECK:       input c#x#4 : UInt
-;CHECK:       output c#y#x#0 : UInt
-;CHECK:       output c#y#x#1 : UInt
-;CHECK:       output c#y#x#2 : UInt
-;CHECK:       input c#y#y : SInt
+;CHECK:       input c$x$0 : UInt
+;CHECK:       input c$x$1 : UInt
+;CHECK:       input c$x$2 : UInt
+;CHECK:       input c$x$3 : UInt
+;CHECK:       input c$x$4 : UInt
+;CHECK:       output c$y$x$0 : UInt
+;CHECK:       output c$y$x$1 : UInt
+;CHECK:       output c$y$x$2 : UInt
+;CHECK:       input c$y$y : SInt
 ;CHECK:       input reset : UInt(1)
-;CHECK:       wire a#x : UInt
-;CHECK:       wire a#y : SInt
-;CHECK:       wire b#x : UInt
-;CHECK:       wire b#y : SInt
-;CHECK:       a#x := b#x
-;CHECK:       b#y := a#y
+;CHECK:       wire a$x : UInt
+;CHECK:       wire a$y : SInt
+;CHECK:       wire b$x : UInt
+;CHECK:       wire b$y : SInt
+;CHECK:       a$x := b$x
+;CHECK:       b$y := a$y
 ;CHECK:       inst i of m
 ;CHECK:       i.reset := reset
-;CHECK:       i.a#x := a#x
-;CHECK:       a#y := i.a#y
-;CHECK:       b#x := i.b#x
-;CHECK:       i.b#y := b#y
-;CHECK:       wire d#0 : UInt
-;CHECK:       wire d#1 : UInt
-;CHECK:       wire d#2 : UInt
-;CHECK:       wire d#3 : UInt
-;CHECK:       wire d#4 : UInt
+;CHECK:       i.a$x := a$x
+;CHECK:       a$y := i.a$y
+;CHECK:       b$x := i.b$x
+;CHECK:       i.b$y := b$y
+;CHECK:       wire d$0 : UInt
+;CHECK:       wire d$1 : UInt
+;CHECK:       wire d$2 : UInt
+;CHECK:       wire d$3 : UInt
+;CHECK:       wire d$4 : UInt
 ;CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index 8eafb8e8..4ab3ba9b 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -7,27 +7,27 @@ circuit top :
       wire j : { x : UInt(32), flip y : UInt(32) }
 
       wire a : { x : UInt(32), flip y : UInt(32) }[2]
-      ; CHECK: wire a#0#x : UInt(32)
-      ; CHECK: wire a#0#y : UInt(32)
-      ; CHECK: wire a#1#x : UInt(32)
-      ; CHECK: wire a#1#y : UInt(32)
+      ; CHECK: wire a$0$x : UInt(32)
+      ; CHECK: wire a$0$y : UInt(32)
+      ; CHECK: wire a$1$x : UInt(32)
+      ; CHECK: wire a$1$y : UInt(32)
 
       accessor b = a[i]
-      ; CHECK: wire b#x : UInt(32)
-      ; CHECK: wire b#y : UInt(32)
-      ; CHECK: b#x := (a#0#x a#1#x)[i]
-      ; CHECK: (a#0#y a#1#y)[i] := b#y
+      ; CHECK: wire b$x : UInt(32)
+      ; CHECK: wire b$y : UInt(32)
+      ; CHECK: b$x := (a$0$x a$1$x)[i]
+      ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
 
       mem m : { x : UInt(32), flip y : UInt(32) }[2]
-      ; CHECK: mem m#x : UInt(32)[2]
-      ; CHECK: mem m#y : UInt(32)[2]
+      ; CHECK: mem m$x : UInt(32)[2]
+      ; CHECK: mem m$y : UInt(32)[2]
 
       accessor c = m[i] ; MALE
-      ; CHECK: accessor c#x = m#x[i]
-      ; CHECK: accessor c#y = m#y[i]
-      ; CHECK: c#x := j#x
-      ; CHECK: j#y := c#y
+      ; CHECK: accessor c$x = m$x[i]
+      ; CHECK: accessor c$y = m$y[i]
+      ; CHECK: c$x := j$x
+      ; CHECK: j$y := c$y
       c := j
 
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index f270bacb..219996fb 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -11,11 +11,11 @@
                wire q : { x : UInt, flip y : SInt }
                r1.init := q    
 
-      ; CHECK: reg r1#x : UInt
-      ; CHECK: reg r1#y : SInt
-      ; CHECK: wire q#x : UInt
-      ; CHECK: wire q#y : SInt
-      ; CHECK: r1#x.init := q#x
-      ; CHECK: q#y := r1#y.init
+      ; CHECK: reg r1$x : UInt
+      ; CHECK: reg r1$y : SInt
+      ; CHECK: wire q$x : UInt
+      ; CHECK: wire q$y : SInt
+      ; CHECK: r1$x.init := q$x
+      ; CHECK: q$y := r1$y.init
 
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir
new file mode 100644
index 00000000..4a516924
--- /dev/null
+++ b/test/passes/resolve-genders/bigenders.fir
@@ -0,0 +1,13 @@
+; RUN: firrtl %s abcdefghipj cg | tee %s.out | FileCheck %s
+
+;CHECK: Resolve Genders
+circuit top :
+   module M :
+      input i : UInt(10)
+      output o : UInt(10)
+      wire w : {x : UInt(10), flip y : UInt(10)}
+      w.x := i
+      w.y := i
+      o := w.x
+      o := w.y
+; CHECK: Finished Resolve Genders