Finished expand whens. started infer widths. added pdf for people to view

4 files changed, 98 insertions, 0 deletions

diff --git a/test/passes/expand-whens/partial-init.fir b/test/passes/expand-whens/partial-init.fir
new file mode 100644
index 00000000..b1da7410
--- /dev/null
+++ b/test/passes/expand-whens/partial-init.fir
@@ -0,0 +1,9 @@
+; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s 
+
+; CHECK: Expand Whens
+circuit top :
+   module top :
+      reg r : UInt(1)[10]
+      r.init.3 := UInt(0)
+
+; CHECK: Finished Expand Whens
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
new file mode 100644
index 00000000..3e1a02f5
--- /dev/null
+++ b/test/passes/infer-widths/gcd.fir
@@ -0,0 +1,45 @@
+; RUN: firrtl %s abcefghipjk cT | tee %s.out | FileCheck %s
+
+;CHECK: Infer Widths
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output q : UInt
+      q := sub-wrap(x, y)
+   module gcd :
+      input a : UInt(16)
+      input b : UInt(16)
+      input e : UInt(1)
+      output z : UInt(16)
+      output v : UInt(1)
+      reg x : UInt
+      reg y : UInt
+      x.init := UInt(0)
+      y.init := UInt(42)
+      when gt(x, y) :
+         inst s of subtracter
+         s.x := x
+         s.y := y
+         x := s.q
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.q
+      when e :
+         x := a
+         y := b
+      v := equal(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+
+; CHECK: Finished Infer Widths
diff --git a/test/passes/jacktest/bundlewire.fir b/test/passes/jacktest/bundlewire.fir
new file mode 100644
index 00000000..0d0f0377
--- /dev/null
+++ b/test/passes/jacktest/bundlewire.fir
@@ -0,0 +1,20 @@
+; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s 
+
+; CHECK: Expand Whens
+
+circuit BundleWire : 
+  module BundleWire : 
+    output in : { y : UInt(32), x : UInt(32) }
+    output outs : { y : UInt(32), x : UInt(32) }[4]
+    
+    wire coords : { y : UInt(32), x : UInt(32) }[4]
+    coords.0 := in
+    outs.0 := coords.0
+    coords.1 := in
+    outs.1 := coords.1
+    coords.2 := in
+    outs.2 := coords.2
+    coords.3 := in
+    outs.3 := coords.3
+
+; CHECK: Finished Expand Whens
diff --git a/test/passes/jacktest/vecshift.fir b/test/passes/jacktest/vecshift.fir
new file mode 100644
index 00000000..9910064d
--- /dev/null
+++ b/test/passes/jacktest/vecshift.fir
@@ -0,0 +1,24 @@
+; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s 
+
+; CHECK: Expand Whens
+
+circuit VecShiftRegister : 
+  module VecShiftRegister : 
+    input load : UInt(1)
+    output out : UInt(4)
+    input shift : UInt(1)
+    input ins : UInt(4)[4]
+    
+    reg delays : UInt(4)[4]
+    when load : 
+      delays.0 := ins.0
+      delays.1 := ins.1
+      delays.2 := ins.2
+      delays.3 := ins.3
+     else : when shift : 
+        delays.0 := ins.0
+        delays.1 := delays.0
+        delays.2 := delays.1
+        delays.3 := delays.2
+    out := delays.3
+; CHECK: Finished Expand Whens