Corrected register init by adding initialization of registers pass after lowering. Finished expand-whens. Needs more thorough testing of instances

3 files changed, 14 insertions, 12 deletions

diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 49fe7757..c62a36c6 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcdefghijk c | tee %s.out | FileCheck %s 
+; RUN: firrtl %s abcefghipj c | tee %s.out | FileCheck %s 
 
 ; CHECK: Expand Whens
 circuit top :
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index b2f052dc..09225143 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -1,33 +1,35 @@
-; RUN: firrtl %s abcdefghijk c | tee %s.out | FileCheck %s 
+; RUN: firrtl %s abcdefghijkp c | tee %s.out | FileCheck %s 
 
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      mem m : UInt(1)[2]
+      mem m :{ x : UInt(1), y : UInt(1) }[2] 
       wire i : UInt(1)
       wire p : UInt(1)
+      wire q : { x : UInt(1), y : UInt(1) }
       when p :
         wire p2 : UInt(1)
+        reg r5 : UInt(1)
         when p2 :
           accessor a = m[i] 
-          i := a
+          q := a
           accessor b = m[i]
-          b := i
+          b := q
         else :
           accessor c = m[i] 
-          i := c
+          q := c
           accessor d = m[i]
-          d := i
+          d := q
       else :
         wire p3 : UInt(1)
         when p3 :
           accessor w = m[i] 
-          i := w
+          q := w
           accessor x = m[i]
-          x := i
+          x := q
         else :
           accessor y = m[i] 
-          i := y
+          q := y
           accessor z = m[i]
-          z := i
+          z := q
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index 7e0a22c0..1f41cacd 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcdef cg | tee %s.out | FileCheck %s
+; RUN: firrtl %s abcef cg | tee %s.out | FileCheck %s
 
 ;CHECK: Resolve Genders
 circuit top :