Merge branch 'master' of github.com:ucb-bar/firrtl into parser

Conflicts:
	TODO
	src/main/stanza/passes.stanza

3 files changed, 101 insertions, 0 deletions

diff --git a/test/passes/jacktest/MemorySearch.fir b/test/passes/jacktest/MemorySearch.fir
new file mode 100644
index 00000000..955d44f2
--- /dev/null
+++ b/test/passes/jacktest/MemorySearch.fir
@@ -0,0 +1,46 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p cd | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit MemorySearch : 
+  module MemorySearch : 
+    input target : UInt(4)
+    output address : UInt(3)
+    input en : UInt(1)
+    output done : UInt(1)
+    
+    node T_35 = UInt(0, 3)
+    reg index : UInt(3)
+    index.init := T_35
+    node T_36 = UInt(0, 1)
+    node T_37 = UInt(4, 3)
+    node T_38 = UInt(15, 4)
+    node T_39 = UInt(14, 4)
+    node T_40 = UInt(2, 2)
+    node T_41 = UInt(5, 3)
+    node T_42 = UInt(13, 4)
+    wire elts : UInt(1)[7]
+    elts.0 := Pad(T_36,?)
+    elts.1 := Pad(T_37,?)
+    elts.2 := Pad(T_38,?)
+    elts.3 := Pad(T_39,?)
+    elts.4 := Pad(T_40,?)
+    elts.5 := Pad(T_41,?)
+    elts.6 := Pad(T_42,?)
+    accessor elt = elts[index]
+    node T_43 = bit-not(en)
+    node T_44 = eq(Pad(elt,?), Pad(target,?))
+    node T_45 = UInt(7, 3)
+    node T_46 = eq(Pad(index,?), Pad(T_45,?))
+    node T_47 = bit-or(T_44, T_46)
+    node end = bit-and(T_43, T_47)
+    when en : 
+      node T_48 = UInt(0, 1)
+      index := Pad(T_48,?)
+    else : 
+      node T_49 = bit-not(end)
+      when T_49 : 
+        node T_50 = UInt(1, 1)
+        node T_51 = add-wrap(Pad(index,?), Pad(T_50,?))
+        index := Pad(T_51,?)
+    done := Pad(end,?)
+    address := Pad(index,?)
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
new file mode 100644
index 00000000..733e2036
--- /dev/null
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -0,0 +1,37 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p cd | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit RegisterVecShift : 
+  module RegisterVecShift : 
+    input load : UInt(1)
+    output out : UInt(4)
+    input shift : UInt(1)
+    input ins : UInt(4)[4]
+    
+    reg delays : UInt(4)[4]
+    when reset : 
+      node T_38 = UInt(0, 4)
+      node T_39 = UInt(0, 4)
+      node T_40 = UInt(0, 4)
+      node T_41 = UInt(0, 4)
+      wire T_42 : UInt(4)[4]
+      T_42.0 := T_38
+      T_42.1 := T_39
+      T_42.2 := T_40
+      T_42.3 := T_41
+      delays := T_42
+    node T_43 = UInt(5, 3)
+    node T_44 = bit-and(Pad(T_43,?), Pad(load,?))
+    node T_45 = UInt(4, 3)
+    node T_46 = eq(Pad(T_44,?), Pad(T_45,?))
+    when T_46 : 
+      delays.0 := Pad(ins.0,?)
+      delays.1 := Pad(ins.1,?)
+      delays.2 := Pad(ins.2,?)
+      delays.3 := Pad(ins.3,?)
+    else : when shift : 
+        delays.0 := Pad(ins.0,?)
+        delays.1 := Pad(delays.0,?)
+        delays.2 := Pad(delays.1,?)
+        delays.3 := Pad(delays.2,?)
+    out := Pad(delays.3,?)
diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir
new file mode 100644
index 00000000..35442ac8
--- /dev/null
+++ b/test/passes/jacktest/Tlb.fir
@@ -0,0 +1,18 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p cTwd | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit Tbl : 
+  module Tbl : 
+    output o : UInt(16)
+    input i : UInt(16)
+    input d : UInt(16)
+    input we : UInt(1)
+    
+    mem m : UInt(10)[256]
+    node T_12 = UInt(0, 1)
+    o := Pad(T_12,?)
+    when we : 
+      accessor T_13 = m[i]
+      T_13 := Pad(d,?)
+    else : 
+      accessor T_14 = m[i]
+      o := Pad(T_14,?)