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authorazidar2015-04-17 13:13:13 -0700
committerazidar2015-04-17 13:13:13 -0700
commit130c6676418e85d5d4dd12a0f0845e912eda8c3e (patch)
tree25b5337fb7a6792ba746f431cec2f43972b67aac /test
parent1b0d51687aaa4d0cf0d52ebf10802ff1064a1cf9 (diff)
Removed excessive debug print statements, added default call to firrtl to generate flo
Diffstat (limited to 'test')
-rw-r--r--test/passes/jacktest/gcd.fir29
1 files changed, 29 insertions, 0 deletions
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
new file mode 100644
index 00000000..a05ef6e6
--- /dev/null
+++ b/test/passes/jacktest/gcd.fir
@@ -0,0 +1,29 @@
+; RUN: firrtl %s abcefghipjklmnoq cw | tee %s.out | FileCheck %s
+
+;CHECK: To Flo
+circuit GCD :
+ module GCD :
+ input b : UInt(16)
+ input a : UInt(16)
+ input e : UInt(1)
+ output z : UInt(16)
+ output v : UInt(1)
+
+ reg x : UInt(16)
+ reg y : UInt(16)
+ node T_17 = gt(x, y)
+ when T_17 :
+ node T_18 = sub-wrap(x, y)
+ x := T_18
+ else :
+ node T_19 = sub-wrap(y, x)
+ y := T_19
+ when e :
+ x := a
+ y := b
+ z := x
+ node T_20 = UInt(0, 1)
+ node T_21 = eq(y, T_20)
+ v := T_21
+
+;CHECK: Finished To Flo