Removed excessive debug print statements, added default call to firrtl to generate flo

5 files changed, 57 insertions, 28 deletions

diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 7d977746..991f7cf6 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -32,7 +32,10 @@ defn main () :
    val c = parse-firrtl(lexed)
    if length(args) >= 4 :
       set-printvars!(to-list(args[3]))
-   run-passes(c,to-list(args[2]))
+   if length(args) >= 3 :
+      run-passes(c,to-list(args[2]))
+   else :
+      run-passes(c,to-list("qabcefghipjklmno"))
 
 main()
 
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 15441950..6ec0c4d2 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -222,7 +222,7 @@ defsyntax firrtl :
          println("Op-symbol is:~" % [op])
          match(get?(operators, ut(op), false)) :
             (op:PrimOp) :
-               println("Op is:~ ~ ~" % [op,op == ADD-OP, op == ADD-UU-OP])
+               ;println("Op is:~ ~ ~" % [op,op == ADD-OP, op == ADD-UU-OP])
                DoPrim(op, es, map(ut, ints), UnknownType())
             (f:False) :
                throw-error $ string-join $ [
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index d2cecabe..24867612 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -263,9 +263,6 @@ defmethod map (f: Type -> Type, e: WIndex) :
 defn temp-elimination (c:Circuit) :
    val h = HashTable<Symbol,Expression>(symbol-hash)
    defn is-temp? (n:Symbol) -> True|False :
-      println(n)
-      println(to-string(n)[0])
-      println(to-string(n)[0] == 'T')
       to-string(n)[0] == 'T'
    defn temp-elim-e (e:Expression) :
       match(map(temp-elim-e,e)) :
@@ -591,11 +588,11 @@ defn resolve-genders (c:Circuit) :
             (e) : map(resolve-expr{_,MALE},e)
 
       var module* = resolve-iter(m)
-      println(genders)
+      ;println(genders)
       while not done? : 
         done? = true
         module* = resolve-iter(m)
-        println(genders)
+        ;println(genders)
       module*
     
    defn resolve-genders (m:Module, c:Circuit) -> Module :
@@ -623,7 +620,7 @@ defn expand-vector (e:Expression) -> List<Expression> :
 defn expand-stmt (s:Stmt) -> Stmt :
    match(s) :
       (s:WDefAccessor) : 
-         println-all(["Matched WDefAcc with " name(s)])
+         ;println-all(["Matched WDefAcc with " name(s)])
          val mem? = match(source(s)) :
             (e:WRef) : kind(e) typeof MemKind
             (e) : false
@@ -780,7 +777,7 @@ defn lower (body:Stmt, table:HashTable<Symbol,List<KeyValue<Expression,Flip>>>)
             headn(tailn(exps,len * value(e)),len)
          (e) : list(KeyValue(e, DEFAULT))
 
-   println(table)
+   ;println(table)
    lower-stmt(body)
 
 defn get-entries (n:Symbol,t:Type) -> List<KeyValue<WRef,Flip>> :
@@ -1491,9 +1488,9 @@ defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Int> :
    ;  2) Remove Cycles
    ;  3) Move to solved if not self-recursive
    val u = make-unique(l)
-   println("======== UNIQUE CONSTRAINTS ========")
-   for x in u do : println(x)
-   println("====================================")
+   ;println("======== UNIQUE CONSTRAINTS ========")
+   ;for x in u do : println(x)
+   ;println("====================================")
 
    val f = HashTable<Symbol,Width>(symbol-hash)
    val o = Vector<Symbol>()
@@ -1611,13 +1608,13 @@ defn build-environment (c:Circuit,m:Module,h:HashTable<Symbol,Type>) -> HashTabl
          
 defn replace-var-widths (c:Circuit,h:HashTable<Symbol,Int>) -> Circuit :
    defn replace-var-widths-w (w:Width) -> Width :
-      println-all(["REPLACE: " w])
+      ;println-all(["REPLACE: " w])
       val w* = match(w) :
          (w:VarWidth) : 
             if key?(h,name(w)) : IntWidth(h[name(w)])
             else: w
          (w) : w
-      println-all(["WITH: " w*])
+      ;println-all(["WITH: " w*])
       w*
 
    val modules* = for m in modules(c) map :
@@ -1661,22 +1658,22 @@ defn infer-widths (c:Circuit) -> Circuit :
    for m in modules(c) do : 
       ports*[name(m)] = remove-unknowns(BundleType(map(to-field,ports(m))))
    val modules* = for m in modules(c) map :
-      println-all(["====== MODULE(" name(m) ") ENV ======"])
+      ;println-all(["====== MODULE(" name(m) ") ENV ======"])
       val h = build-environment(c,m,deepcopy(ports*))
-      for x in h do: println(x)
-      println-all(["====================================="])
+      ;for x in h do: println(x)
+      ;println-all(["====================================="])
       val m* = gen-constraints(m,h,v)
-      println-all(["====== MODULE(" name(m) ") ======"])
-      println(m*)
-      println-all(["====================================="])
+      ;println-all(["====== MODULE(" name(m) ") ======"])
+      ;println(m*)
+      ;println-all(["====================================="])
       m*
-   println("======== ALL CONSTRAINTS ========")
-   for x in v do : println(x)
-   println("=================================")
+   ;println("======== ALL CONSTRAINTS ========")
+   ;for x in v do : println(x)
+   ;println("=================================")
    val h = solve-constraints(to-list(v))
-   println("======== SOLVED CONSTRAINTS ========")
-   for x in h do : println(x)
-   println("====================================")
+   ;println("======== SOLVED CONSTRAINTS ========")
+   ;for x in h do : println(x)
+   ;println("====================================")
    replace-var-widths(Circuit(modules*,main(c)),h)
 
 
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza
index a7fc15ac..b42380e6 100644
--- a/src/main/stanza/primop.stanza
+++ b/src/main/stanza/primop.stanza
@@ -21,7 +21,7 @@ public defn lower-and-type-primop (e:DoPrim) -> DoPrim :
          (t:SIntType) : s()
          (t) : UnknownType()
 
-   println-all(["Inferencing primop type: " e])
+   ;println-all(["Inferencing primop type: " e])
    switch {op(e) == _} :
       ADD-OP           : 
          DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $
@@ -274,7 +274,7 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type :
    defn sum (l:List<Expression>) : 
       add-c(PlusWidth(width!(l[0]),width!(l[1])))
 
-   println-all(["Looking at " op(e) " with inputs " args(e)])
+   ;println-all(["Looking at " op(e) " with inputs " args(e)])
    switch {op(e) == _} :
       ADD-UU-OP : mp1(args(e))
       ADD-US-OP : mp1(args(e))
diff --git a/test/passes/jacktest/gcd.fir b/test/passes/jacktest/gcd.fir
new file mode 100644
index 00000000..a05ef6e6
--- /dev/null
+++ b/test/passes/jacktest/gcd.fir
@@ -0,0 +1,29 @@
+; RUN: firrtl %s abcefghipjklmnoq cw | tee %s.out | FileCheck %s
+
+;CHECK: To Flo
+circuit GCD : 
+  module GCD : 
+    input b : UInt(16)
+    input a : UInt(16)
+    input e : UInt(1)
+    output z : UInt(16)
+    output v : UInt(1)
+    
+    reg x : UInt(16)
+    reg y : UInt(16)
+    node T_17 = gt(x, y)
+    when T_17 : 
+      node T_18 = sub-wrap(x, y)
+      x := T_18
+    else : 
+      node T_19 = sub-wrap(y, x)
+      y := T_19
+    when e : 
+      x := a
+      y := b
+    z := x
+    node T_20 = UInt(0, 1)
+    node T_21 = eq(y, T_20)
+    v := T_21
+
+;CHECK: Finished To Flo