Fixed width inference bug where later constraints on the output width were not propogating to the input widths, for primops

1 files changed, 18 insertions, 0 deletions

diff --git a/test/passes/jacktest/Tlb.fir b/test/passes/jacktest/Tlb.fir
new file mode 100644
index 00000000..35442ac8
--- /dev/null
+++ b/test/passes/jacktest/Tlb.fir
@@ -0,0 +1,18 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p cTwd | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit Tbl : 
+  module Tbl : 
+    output o : UInt(16)
+    input i : UInt(16)
+    input d : UInt(16)
+    input we : UInt(1)
+    
+    mem m : UInt(10)[256]
+    node T_12 = UInt(0, 1)
+    o := Pad(T_12,?)
+    when we : 
+      accessor T_13 = m[i]
+      T_13 := Pad(d,?)
+    else : 
+      accessor T_14 = m[i]
+      o := Pad(T_14,?)