Added debug print statements to dump fields from nodes, and updated tests to call firrtl correctly to enable/disable them

6 files changed, 55 insertions, 40 deletions

diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index b261f0d1..4fdc9ab1 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcde | tee %s.out | FileCheck %s
+; RUN: firrtl %s abcde ct | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Types
 circuit top :
@@ -7,6 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-mod(x, y)
+      ;CHECK: z@<t:UInt> := sub-mod(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
    module gcd :
       input a : UInt(16)
       input b : UInt(16)
@@ -19,10 +20,16 @@ circuit top :
       x.init := UInt(0)
       y.init := UInt(42)
       when greater(x, y) :
+      ;CHECK: when greater(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
+         ;CHECK: inst s of subtracter@<t:{input x : UInt@<t:UInt>, input y : UInt@<t:UInt>, output z : UInt@<t:UInt>, input reset : UInt(1)@<t:UInt(1)>}>
          s.x := x
          s.y := y
          x := s.z
+         ;CHECK: s@<t:{input x : UInt@<t:UInt>, input y : UInt@<t:UInt>, output z : UInt@<t:UInt>, input reset : UInt(1)@<t:UInt(1)>}>.reset@<t:UInt(1)> := reset@<t:UInt(1)>
+         ;CHECK: s@<t:{input x : UInt@<t:UInt>, input y : UInt@<t:UInt>, output z : UInt@<t:UInt>, input reset : UInt(1)@<t:UInt(1)>}>.x@<t:UInt> := x@<t:UInt>
+         ;CHECK: s@<t:{input x : UInt@<t:UInt>, input y : UInt@<t:UInt>, output z : UInt@<t:UInt>, input reset : UInt(1)@<t:UInt(1)>}>.y@<t:UInt> := y@<t:UInt>
+         ;CHECK: x@<t:UInt> := s@<t:{input x : UInt@<t:UInt>, input y : UInt@<t:UInt>, output z : UInt@<t:UInt>, input reset : UInt(1)@<t:UInt(1)>}>.z@<t:UInt>
       else :
          inst s2 of subtracter
          s2.x := x
@@ -32,6 +39,7 @@ circuit top :
          x := a
          y := b
       v := equal(v, UInt(0))
+      ;CHECK: v@<t:UInt(1)> := equal(v@<t:UInt(1)>, UInt(0))@<t:UInt>
       z := x
    module top :
       input a : UInt(16)
@@ -43,4 +51,4 @@ circuit top :
       i.e := UInt(1)
       z := i.z
 
-
+; CHECK: Finished Infer Types
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index dc47d9c6..244853cf 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -1,9 +1,10 @@
-; RUN: firrtl %s abcde | tee %s.out | FileCheck %s
+; RUN: firrtl %s abcde ct | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Types
 circuit top :
    module top :
       wire io : {input x : UInt, output y : UInt}
-      wire a : UInt 
-      a := io.x
-
+      node a = io.x
+;CHECK: wire io : {input x : UInt@<t:UInt>, output y : UInt@<t:UInt>}@<t:{input x : UInt@<t:UInt>, output y : UInt@<t:UInt>}>
+;CHECK: node a = io@<t:{input x : UInt@<t:UInt>, output y : UInt@<t:UInt>}>.x@<t:UInt>
+;CHECK: Finished Infer Types
diff --git a/test/passes/initialize-register/begin.fir b/test/passes/initialize-register/begin.fir
index 4f64b071..fab45e64 100644
--- a/test/passes/initialize-register/begin.fir
+++ b/test/passes/initialize-register/begin.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcd | tee %s.out | FileCheck %s 
+; RUN: firrtl %s abcd c | tee %s.out | FileCheck %s 
 
 ; CHECK: Initialize Registers
          circuit top :
@@ -9,16 +9,18 @@
 
                reg r1 : UInt
 ; CHECK:       wire [[R1:gen[0-9]*]] : UInt
-; CHECK:       n:[[R1]] := Null
+; CHECK:       [[R1]] := Null
 
                reg r2 : UInt
                r2.init := UInt(0)
 ; CHECK-NOT:   r2.init := UInt(0)
 ; CHECK:       wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:   reg:r2 := n:[[R2]]
-; CHECK:       n:[[R2]] := Null
-; CHECK:       n:[[R2]] := UInt(0)
+; CHECK-NOT:   r2 := [[R2]]
+; CHECK:       [[R2]] := Null
+; CHECK:       [[R2]] := UInt(0)
       
-; CHECK:       when port:reset :
-; CHECK-DAG:      reg:r1 := n:[[R1]]
-; CHECK-DAG:      reg:r2 := n:[[R2]]
+; CHECK:       when reset :
+; CHECK-DAG:      r1 := [[R1]]
+; CHECK-DAG:      r2 := [[R2]]
+
+; CHECK: Finished Initialize Registers
diff --git a/test/passes/initialize-register/when.fir b/test/passes/initialize-register/when.fir
index c563d639..4e2bef79 100644
--- a/test/passes/initialize-register/when.fir
+++ b/test/passes/initialize-register/when.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcd | tee %s.out | FileCheck %s 
+; RUN: firrtl %s abcd c | tee %s.out | FileCheck %s 
 
 ; CHECK: Initialize Registers
          circuit top :
@@ -10,32 +10,34 @@
                   reg r1: UInt
                   r1.init := UInt(12)
 ; CHECK:          wire [[R1:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r1 := n:[[R1]]
-; CHECK:          n:[[R1]] := Null
-; CHECK:          n:[[R1]] := UInt(12)
+; CHECK-NOT:      r1 := [[R1]]
+; CHECK:          [[R1]] := Null
+; CHECK:          [[R1]] := UInt(12)
 ; CHECK-NOT:      r1.init := UInt(12)
                   reg r2: UInt
 ; CHECK:          wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r2 := n:[[R2]]
-; CHECK:          n:[[R2]] := Null
+; CHECK-NOT:      r2 := [[R2]]
+; CHECK:          [[R2]] := Null
 
-; CHECK:          when port:reset :
-; CHECK-DAG:         reg:r2 := n:[[R2]]
-; CHECK-DAG:         reg:r1 := n:[[R1]]
+; CHECK:          when reset :
+; CHECK-DAG:         r2 := [[R2]]
+; CHECK-DAG:         r1 := [[R1]]
                else :
                   reg r1: UInt
                   r1.init := UInt(12)
 ; CHECK:          wire [[R1:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r1 := n:[[R1]]
-; CHECK:          n:[[R1]] := Null
-; CHECK:          n:[[R1]] := UInt(12)
+; CHECK-NOT:      r1 := [[R1]]
+; CHECK:          [[R1]] := Null
+; CHECK:          [[R1]] := UInt(12)
 ; CHECK-NOT:      r1.init := UInt(12)
 
                   reg r2: UInt
 ; CHECK:          wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r2 := n:[[R2]]
-; CHECK:          n:[[R2]] := Null
+; CHECK-NOT:      r2 := [[R2]]
+; CHECK:          [[R2]] := Null
 
-; CHECK:          when port:reset :
-; CHECK-DAG:         reg:r2 := n:[[R2]]
-; CHECK-DAG:         reg:r1 := n:[[R1]]
+; CHECK:          when reset :
+; CHECK-DAG:         r2 := [[R2]]
+; CHECK-DAG:         r1 := [[R1]]
+
+; CHECK: Finished Initialize Registers
diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir
index 23a1232a..c6487c8d 100644
--- a/test/passes/make-explicit-reset/mix-reset.fir
+++ b/test/passes/make-explicit-reset/mix-reset.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abc | tee %s.out | FileCheck %s
+; RUN: firrtl %s abc c | tee %s.out | FileCheck %s
 
 ; CHECK: Make Explicit Reset
 circuit top :
@@ -7,14 +7,14 @@ circuit top :
       input x : UInt(16)
       output y : UInt(16)
       inst b of B
-      ;CHECK: inst:b.reset := port:reset
+      ;CHECK: b.reset := reset
    module B :
       input reset : UInt(1)
       ;CHECK: input reset : UInt(1)
       input x : UInt(16)
       output y : UInt(16)
       inst c of C
-      ;CHECK: inst:c.reset := port:reset
+      ;CHECK: c.reset := reset
    module C :
       ;CHECK: input reset : UInt(1)
       input a : UInt(16)
@@ -25,4 +25,5 @@ circuit top :
       input b : UInt(16)
       output z : UInt
       inst a of A
-      ;CHECK: inst:a.reset := port:reset
+      ;CHECK: a.reset := reset
+;CHECK: Finished Make Explicit Reset
diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir
index 83091f67..b06da6c5 100644
--- a/test/passes/resolve-kinds/gcd.fir
+++ b/test/passes/resolve-kinds/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s ab | tee %s.out | FileCheck %s
+; RUN: firrtl %s ab ck | tee %s.out | FileCheck %s
 
 ; CHECK: Resolve Kinds
 circuit top :
@@ -7,7 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-mod(x, y)
-; CHECK: port:z := sub-mod(port:x, port:y)
+      ;CHECK: z@<k:port> := sub-mod(x@<k:port>, y@<k:port>)
    module gcd :
       input a : UInt(16)
       input b : UInt(16)
@@ -21,7 +21,7 @@ circuit top :
       when greater(x, y) :
          inst s of subtracter
          s.x := x
-; CHECK: inst:s.x := reg:x
+         ;CHECK: s@<k:inst>.x := x@<k:reg>
          s.y := y
          x := s.z
       else :
@@ -39,11 +39,12 @@ circuit top :
       input b : UInt(16)
       output z : UInt
       inst i of gcd
-; CHECK: inst i of module:gcd
+      ;CHECK: inst i of gcd@<k:module>
       i.a := a
       i.b := b
       i.e := UInt(1)
       z := i.z
-; CHECK: port:z := inst:i.z
+      ;CHECK: z@<k:port> := i@<k:inst>.z
+; CHECK: Finished Resolve Kinds