Added debug print statements to dump fields from nodes, and updated tests to call firrtl correctly to enable/disable them

12 files changed, 152 insertions, 65 deletions

diff --git a/TODO b/TODO
index 46d0f5bf..d09abb1a 100644
--- a/TODO
+++ b/TODO
@@ -1,12 +1,31 @@
 
 TODO 
-   Make stanza a git repo
-   Write installation instructions for stanza
-   Need 2 different prints, one with IR-internal information, and another that matches correct FIRRTL
+   Update print defmethods to correctly print depending on global variables
+   Update tests to invoke compiler correctly, and fix matches
    Figure out how types and widths propogate for all updated primops
-   node not parsed for stmts
+   Write infer-types pass
+   Update spec
+      change concrete syntactical names of structural elements
+      change direction names for bundle fields
+      add new field for sequential or combinational
+      play with non-implicit growth
+      remove generics, add all combinations (adduu, addus, addss, ...)
+      add assertions
+      add convert to primop
+      remove type from node in statement
+   Future questions to address in spec:
+      Introduction – motivation, and intended usage
+      Philosophical justifications for all constructs
+      More introduction for types, e.g. what is a ground type?
+      What is a statement? What is an expression? What is a memory? Difference between vector type and memory? What are accessors for?
+      Why would I ever write an empty statement? Mainly for use by compiler/passes
+      What is a structural element? Duplication?
+      Subtracting two unsigned numbers… Should talk to a math guy to figure it out
+      What are shift left and shift right operations? HW doesn’t have these concepts. Need justification.
+      What is lowered form? What is it for?
+
 
 Tests:
    Error if declare anything other than module in circuit
    Error if incorrectly assign stuff, like use = instead of :=
-
+   Error: Node not parsed for stmts
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 9ec4b666..259bba10 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -83,6 +83,9 @@ public defstruct DefInstance <: Stmt :
 public defstruct DefMemory <: Stmt :
    name: Symbol
    type: VectorType
+public defstruct DefNode <: Stmt :
+   name: Symbol
+   value: Expression
 public defstruct DefAccessor <: Stmt :
    name: Symbol
    source: Expression
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 8904bd27..fe940a9f 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -18,16 +18,20 @@ defpackage firrtl-main :
    import stanza.parser
    import firrtl.ir-utils
 
-public var PRINT-TYPES : True|False = false
+defn set-printvars! (p:List<Char>) :
+   if contains(p,'t') : PRINT-TYPES = true
+   if contains(p,'k') : PRINT-KINDS = true
+   if contains(p,'w') : PRINT-WIDTHS = true
+   if contains(p,'c') : PRINT-CIRCUITS = true
 
 defn main () :
    val arg = commandline-arguments()
    val args = split(arg,' ')
    val lexed = lex-file(args[1])
    val c = parse-firrtl(lexed)
-   ;println(c)
+   if length(args) >= 4 :
+      set-printvars!(to-list(args[3]))
    run-passes(c,to-list(args[2]))
 
 main()
 
-
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 176a812c..34dbcec7 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -112,6 +112,8 @@ rd.defsyntax firrtl :
          DefMemory(ut(name), type)
       (inst ?name:#symbol of ?module:#exp) :
          DefInstance(ut(name), module)
+      (node ?name:#symbol = ?exp:#exp) :
+         DefNode(ut(name), exp)
       (accessor ?name:#symbol = ?source:#exp (@get ?index:#exp)) :
          DefAccessor(ut(name), source, index)
       ((?body:#comm ...)) :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 7fe61ff2..1aaa264a 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -3,6 +3,10 @@ defpackage firrtl.ir-utils :
    import verse
    import firrtl.ir2
 
+;============== DEBUG STUFF =============================
+
+public defmulti print-debug (o:OutputStream, e:Expression|Stmt|Type|Element|Port) -> False
+
 ;============== PRINTERS ===================================
 defmethod print (o:OutputStream, d:Direction) :
    print{o, _} $
@@ -56,6 +60,7 @@ defmethod print (o:OutputStream, e:Expression) :
          print(o, ")")
       (e:ReadPort) : print-all(o, ["ReadPort(" mem(e) ", " index(e) ")"])
       (e:Null) : print-all(o, ["Null"])
+   print-debug(o,e)
 
 defmethod print (o:OutputStream, c:Stmt) :
    match(c) :
@@ -74,6 +79,8 @@ defmethod print (o:OutputStream, c:Stmt) :
          print-all(["mem " name(c) " : " type(c)])
       (c:DefInstance) :
          print-all(["inst " name(c) " of " module(c)])
+      (c:DefNode) :
+         print-all(["node " name(c) " = " value(c)])      
       (c:DefAccessor) :
          print-all(["accessor " name(c) " = " source(c) "[" index(c) "]"])      
       (c:Conditionally) :
@@ -88,6 +95,7 @@ defmethod print (o:OutputStream, c:Stmt) :
          print-all(o, [loc(c) " := " exp(c)])
       (c:EmptyStmt) :
          print(o, "skip")
+   print-debug(o,c)
 
 defmethod print (o:OutputStream, e:Element) :
    match(e) :
@@ -103,6 +111,7 @@ defmethod print (o:OutputStream, e:Element) :
          print-all(o, ["Instance(" module(e) ", "])
          print-all(o, join(ports(e), ", "))
          print(o, ")")
+   print-debug(o,e)
 
 defmethod print (o:OutputStream, p:WritePort) :
    print-all(o, [index(p) " => WritePort(" value(p) ", " enable(p) ")"])
@@ -123,9 +132,11 @@ defmethod print (o:OutputStream, t:Type) :
          print(o, "}")
       (t:VectorType) :
          print-all(o, [type(t) "[" size(t) "]"])
+   print-debug(o,t)
 
 defmethod print (o:OutputStream, p:Port) :
    print-all(o, [direction(p) " " name(p) " : " type(p)])
+   print-debug(o,p)
 
 defmethod print (o:OutputStream, m:Module) :
    println-all(o, ["module " name(m) " :"])
@@ -207,6 +218,7 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
                            key(entry) => map(f, value(entry))
          LetRec(entries*, body(c))                  
       (c:DefAccessor) : DefAccessor(name(c), f(source(c)), f(index(c)))
+      (c:DefNode) : DefNode(name(c), f(value(c)))
       (c:DefInstance) : DefInstance(name(c), f(module(c)))
       (c:Conditionally) : Conditionally(f(pred(c)), conseq(c), alt(c))
       (c:Connect) : Connect(f(loc(c)), f(exp(c)))
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 4a5634d0..25ce27bd 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -49,33 +49,61 @@ defstruct WDefAccessor <: Stmt :
    dir: Direction
 
 ;================ WORKING IR UTILS =========================
+;============== DEBUG STUFF =============================
+public var PRINT-TYPES : True|False = false
+public var PRINT-KINDS : True|False = false
+public var PRINT-WIDTHS : True|False = false
+public var PRINT-CIRCUITS : True|False = false
 ;=== Printers ===
 defmethod print (o:OutputStream, k:Kind) :
    print{o, _} $
    match(k) :
-      (k:RegKind) : "reg:"
-      (k:AccessorKind) : "accessor:"
-      (k:PortKind) : "port:"
-      (k:MemKind) : "mem:"
-      (k:NodeKind) : "n:"
-      (k:ModuleKind) : "module:"
-      (k:InstanceKind) : "inst:"
-      (k:StructuralMemKind) : "smem:"
-
+      (k:RegKind) : "reg"
+      (k:AccessorKind) : "accessor"
+      (k:PortKind) : "port"
+      (k:MemKind) : "mem"
+      (k:NodeKind) : "n"
+      (k:ModuleKind) : "module"
+      (k:InstanceKind) : "inst"
+      (k:StructuralMemKind) : "smem"
+
+defn hasWidth (e:Expression|Stmt|Type|Element|Port) :
+   e typeof UIntType|SIntType|UIntValue|SIntValue
+
+defn hasType (e:Expression|Stmt|Type|Element|Port) :
+   e typeof Ref|Field|Index|DoPrim|ReadPort|WRef|WField
+      |WIndex|DefWire|DefRegister|DefMemory|Register
+      |Memory|Node|Instance|VectorType|Port
+
+defn hasKind (e:Expression|Stmt|Type|Element|Port) :
+   e typeof WRef
+
+defn any-debug? (e:Expression|Stmt|Type|Element|Port) : 
+   (hasType(e) and PRINT-TYPES) or
+   (hasWidth(e) and PRINT-WIDTHS) or
+   (hasKind(e) and PRINT-KINDS)
+
+defmethod print-debug (o:OutputStream, e:Expression|Stmt|Type|Element|Port) :
+   if any-debug?(e) : print(o,"@")
+   if PRINT-KINDS and hasKind(e) : print-all(o,["<k:" kind(e as ?) ">"])
+   if PRINT-TYPES and hasType(e) : print-all(o,["<t:" type(e as ?) ">"])
+   if PRINT-WIDTHS and hasWidth(e): print-all(o,["<w:" width(e as ?) ">"])
+      
 defmethod print (o:OutputStream, e:WRef) :
-   if PRINT-TYPES :
-      print-all(o,[kind(e) name(e) ":" type(e)])
-   else : 
-      print-all(o,[kind(e) name(e)])
+   print(o,name(e))
+   print-debug(o,e as ?)
 
 defmethod print (o:OutputStream, e:WField) :
    print-all(o,[exp(e) "." name(e)])
+   print-debug(o,e as ?)
 
 defmethod print (o:OutputStream, e:WIndex) :
    print-all(o,[exp(e) "." value(e)])
+   print-debug(o,e as ?)
 
 defmethod print (o:OutputStream, s:WDefAccessor) :
-  print-all(o,[dir(s) " accessor " name(s) " = " source(s) "[" index(s) "]"])
+   print-all(o,[dir(s) " accessor " name(s) " = " source(s) "[" index(s) "]"])
+   print-debug(o,s)
 
 defmethod map (f: Expression -> Expression, e: WField) :
    WField(f(exp(e)), name(e), type(e), dir(e))
@@ -1896,10 +1924,14 @@ defn inline-instances (c:Circuit) :
 ;============= DRIVER ======================================
 public defn run-passes (c: Circuit, p: List<Char>) :
    var c*:Circuit = c
+   println("Compiling!")
+   if PRINT-CIRCUITS : println("Original Circuit")
+   if PRINT-CIRCUITS : print(c)
    defn do-stage (name:String, f: Circuit -> Circuit) :
-      println(name)
+      if PRINT-CIRCUITS : println(name)
       c* = f(c*)
-      println(c*)
+      if PRINT-CIRCUITS : print(c*)
+      if PRINT-CIRCUITS : println-all(["Finished " name "\n"])
 
   ; Early passes:
   ;  If modules have a reset defined, must be an INPUT and UInt(1)
@@ -1919,7 +1951,7 @@ public defn run-passes (c: Circuit, p: List<Char>) :
    if contains(p,'n') : do-stage("Pad Widths", pad-widths)
    if contains(p,'o') : do-stage("Inline Instances", inline-instances)
 
-   println("\n\n\n\n")
+   println("Done!")
 
 
  ;;  println("Shim for Jonathan's Passes")
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index b261f0d1..4fdc9ab1 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcde | tee %s.out | FileCheck %s
+; RUN: firrtl %s abcde ct | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Types
 circuit top :
@@ -7,6 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-mod(x, y)
+      ;CHECK: z@<t:UInt> := sub-mod(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
    module gcd :
       input a : UInt(16)
       input b : UInt(16)
@@ -19,10 +20,16 @@ circuit top :
       x.init := UInt(0)
       y.init := UInt(42)
       when greater(x, y) :
+      ;CHECK: when greater(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
+         ;CHECK: inst s of subtracter@<t:{input x : UInt@<t:UInt>, input y : UInt@<t:UInt>, output z : UInt@<t:UInt>, input reset : UInt(1)@<t:UInt(1)>}>
          s.x := x
          s.y := y
          x := s.z
+         ;CHECK: s@<t:{input x : UInt@<t:UInt>, input y : UInt@<t:UInt>, output z : UInt@<t:UInt>, input reset : UInt(1)@<t:UInt(1)>}>.reset@<t:UInt(1)> := reset@<t:UInt(1)>
+         ;CHECK: s@<t:{input x : UInt@<t:UInt>, input y : UInt@<t:UInt>, output z : UInt@<t:UInt>, input reset : UInt(1)@<t:UInt(1)>}>.x@<t:UInt> := x@<t:UInt>
+         ;CHECK: s@<t:{input x : UInt@<t:UInt>, input y : UInt@<t:UInt>, output z : UInt@<t:UInt>, input reset : UInt(1)@<t:UInt(1)>}>.y@<t:UInt> := y@<t:UInt>
+         ;CHECK: x@<t:UInt> := s@<t:{input x : UInt@<t:UInt>, input y : UInt@<t:UInt>, output z : UInt@<t:UInt>, input reset : UInt(1)@<t:UInt(1)>}>.z@<t:UInt>
       else :
          inst s2 of subtracter
          s2.x := x
@@ -32,6 +39,7 @@ circuit top :
          x := a
          y := b
       v := equal(v, UInt(0))
+      ;CHECK: v@<t:UInt(1)> := equal(v@<t:UInt(1)>, UInt(0))@<t:UInt>
       z := x
    module top :
       input a : UInt(16)
@@ -43,4 +51,4 @@ circuit top :
       i.e := UInt(1)
       z := i.z
 
-
+; CHECK: Finished Infer Types
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index dc47d9c6..244853cf 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -1,9 +1,10 @@
-; RUN: firrtl %s abcde | tee %s.out | FileCheck %s
+; RUN: firrtl %s abcde ct | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Types
 circuit top :
    module top :
       wire io : {input x : UInt, output y : UInt}
-      wire a : UInt 
-      a := io.x
-
+      node a = io.x
+;CHECK: wire io : {input x : UInt@<t:UInt>, output y : UInt@<t:UInt>}@<t:{input x : UInt@<t:UInt>, output y : UInt@<t:UInt>}>
+;CHECK: node a = io@<t:{input x : UInt@<t:UInt>, output y : UInt@<t:UInt>}>.x@<t:UInt>
+;CHECK: Finished Infer Types
diff --git a/test/passes/initialize-register/begin.fir b/test/passes/initialize-register/begin.fir
index 4f64b071..fab45e64 100644
--- a/test/passes/initialize-register/begin.fir
+++ b/test/passes/initialize-register/begin.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcd | tee %s.out | FileCheck %s 
+; RUN: firrtl %s abcd c | tee %s.out | FileCheck %s 
 
 ; CHECK: Initialize Registers
          circuit top :
@@ -9,16 +9,18 @@
 
                reg r1 : UInt
 ; CHECK:       wire [[R1:gen[0-9]*]] : UInt
-; CHECK:       n:[[R1]] := Null
+; CHECK:       [[R1]] := Null
 
                reg r2 : UInt
                r2.init := UInt(0)
 ; CHECK-NOT:   r2.init := UInt(0)
 ; CHECK:       wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:   reg:r2 := n:[[R2]]
-; CHECK:       n:[[R2]] := Null
-; CHECK:       n:[[R2]] := UInt(0)
+; CHECK-NOT:   r2 := [[R2]]
+; CHECK:       [[R2]] := Null
+; CHECK:       [[R2]] := UInt(0)
       
-; CHECK:       when port:reset :
-; CHECK-DAG:      reg:r1 := n:[[R1]]
-; CHECK-DAG:      reg:r2 := n:[[R2]]
+; CHECK:       when reset :
+; CHECK-DAG:      r1 := [[R1]]
+; CHECK-DAG:      r2 := [[R2]]
+
+; CHECK: Finished Initialize Registers
diff --git a/test/passes/initialize-register/when.fir b/test/passes/initialize-register/when.fir
index c563d639..4e2bef79 100644
--- a/test/passes/initialize-register/when.fir
+++ b/test/passes/initialize-register/when.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abcd | tee %s.out | FileCheck %s 
+; RUN: firrtl %s abcd c | tee %s.out | FileCheck %s 
 
 ; CHECK: Initialize Registers
          circuit top :
@@ -10,32 +10,34 @@
                   reg r1: UInt
                   r1.init := UInt(12)
 ; CHECK:          wire [[R1:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r1 := n:[[R1]]
-; CHECK:          n:[[R1]] := Null
-; CHECK:          n:[[R1]] := UInt(12)
+; CHECK-NOT:      r1 := [[R1]]
+; CHECK:          [[R1]] := Null
+; CHECK:          [[R1]] := UInt(12)
 ; CHECK-NOT:      r1.init := UInt(12)
                   reg r2: UInt
 ; CHECK:          wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r2 := n:[[R2]]
-; CHECK:          n:[[R2]] := Null
+; CHECK-NOT:      r2 := [[R2]]
+; CHECK:          [[R2]] := Null
 
-; CHECK:          when port:reset :
-; CHECK-DAG:         reg:r2 := n:[[R2]]
-; CHECK-DAG:         reg:r1 := n:[[R1]]
+; CHECK:          when reset :
+; CHECK-DAG:         r2 := [[R2]]
+; CHECK-DAG:         r1 := [[R1]]
                else :
                   reg r1: UInt
                   r1.init := UInt(12)
 ; CHECK:          wire [[R1:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r1 := n:[[R1]]
-; CHECK:          n:[[R1]] := Null
-; CHECK:          n:[[R1]] := UInt(12)
+; CHECK-NOT:      r1 := [[R1]]
+; CHECK:          [[R1]] := Null
+; CHECK:          [[R1]] := UInt(12)
 ; CHECK-NOT:      r1.init := UInt(12)
 
                   reg r2: UInt
 ; CHECK:          wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:      reg:r2 := n:[[R2]]
-; CHECK:          n:[[R2]] := Null
+; CHECK-NOT:      r2 := [[R2]]
+; CHECK:          [[R2]] := Null
 
-; CHECK:          when port:reset :
-; CHECK-DAG:         reg:r2 := n:[[R2]]
-; CHECK-DAG:         reg:r1 := n:[[R1]]
+; CHECK:          when reset :
+; CHECK-DAG:         r2 := [[R2]]
+; CHECK-DAG:         r1 := [[R1]]
+
+; CHECK: Finished Initialize Registers
diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir
index 23a1232a..c6487c8d 100644
--- a/test/passes/make-explicit-reset/mix-reset.fir
+++ b/test/passes/make-explicit-reset/mix-reset.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s abc | tee %s.out | FileCheck %s
+; RUN: firrtl %s abc c | tee %s.out | FileCheck %s
 
 ; CHECK: Make Explicit Reset
 circuit top :
@@ -7,14 +7,14 @@ circuit top :
       input x : UInt(16)
       output y : UInt(16)
       inst b of B
-      ;CHECK: inst:b.reset := port:reset
+      ;CHECK: b.reset := reset
    module B :
       input reset : UInt(1)
       ;CHECK: input reset : UInt(1)
       input x : UInt(16)
       output y : UInt(16)
       inst c of C
-      ;CHECK: inst:c.reset := port:reset
+      ;CHECK: c.reset := reset
    module C :
       ;CHECK: input reset : UInt(1)
       input a : UInt(16)
@@ -25,4 +25,5 @@ circuit top :
       input b : UInt(16)
       output z : UInt
       inst a of A
-      ;CHECK: inst:a.reset := port:reset
+      ;CHECK: a.reset := reset
+;CHECK: Finished Make Explicit Reset
diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir
index 83091f67..b06da6c5 100644
--- a/test/passes/resolve-kinds/gcd.fir
+++ b/test/passes/resolve-kinds/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl %s ab | tee %s.out | FileCheck %s
+; RUN: firrtl %s ab ck | tee %s.out | FileCheck %s
 
 ; CHECK: Resolve Kinds
 circuit top :
@@ -7,7 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-mod(x, y)
-; CHECK: port:z := sub-mod(port:x, port:y)
+      ;CHECK: z@<k:port> := sub-mod(x@<k:port>, y@<k:port>)
    module gcd :
       input a : UInt(16)
       input b : UInt(16)
@@ -21,7 +21,7 @@ circuit top :
       when greater(x, y) :
          inst s of subtracter
          s.x := x
-; CHECK: inst:s.x := reg:x
+         ;CHECK: s@<k:inst>.x := x@<k:reg>
          s.y := y
          x := s.z
       else :
@@ -39,11 +39,12 @@ circuit top :
       input b : UInt(16)
       output z : UInt
       inst i of gcd
-; CHECK: inst i of module:gcd
+      ;CHECK: inst i of gcd@<k:module>
       i.a := a
       i.b := b
       i.e := UInt(1)
       z := i.z
-; CHECK: port:z := inst:i.z
+      ;CHECK: z@<k:port> := i@<k:inst>.z
+; CHECK: Finished Resolve Kinds