Finished first two parts of expand-whens pass. Fixed inits by adding WRegInit and removing Null and initialize-register pass

6 files changed, 59 insertions, 70 deletions

diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
new file mode 100644
index 00000000..ce14c7ba
--- /dev/null
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -0,0 +1,27 @@
+; RUN: firrtl %s abcdefghi c | tee %s.out | FileCheck %s
+
+; CHECK: Expand Indexed Connects
+circuit top :
+   module q :
+      wire i : UInt
+      wire j : UInt
+
+      wire a : { x : UInt(32), flip y : UInt(32) }[2]
+      ; CHECK: wire a#0#x : UInt(32)
+      ; CHECK: wire a#0#y : UInt(32)
+      ; CHECK: wire a#1#x : UInt(32)
+      ; CHECK: wire a#1#y : UInt(32)
+
+      accessor b = a[i]
+      ; CHECK: wire b#x : UInt(32)
+      ; CHECK: wire b#y : UInt(32)
+      ; CHECK: b#x := a#0#x
+      ; CHECK: when equal-uu(i, UInt(1)) :
+      ; CHECK:    b#x := a#1#x
+      ; CHECK: a#0#y := b#y
+      ; CHECK: when equal-uu(i, UInt(1)) :
+      ; CHECK:    a#1#y := b#y
+      j := b
+      
+; CHECK: Finished Expand Indexed Connects
+
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 78c59493..9745d087 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -1,3 +1,6 @@
+; RUN: firrtl %s abcdefghijk c | tee %s.out | FileCheck %s 
+
+; CHECK: Expand Whens
 circuit top :
    module top :
       mem m : UInt(1)[2]
@@ -13,3 +16,5 @@ circuit top :
         i := c
         accessor d = m[i] 
         d := i
+
+; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index 16fae1e2..b2f052dc 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -1,3 +1,6 @@
+; RUN: firrtl %s abcdefghijk c | tee %s.out | FileCheck %s 
+
+; CHECK: Expand Whens
 circuit top :
    module top :
       mem m : UInt(1)[2]
@@ -16,7 +19,8 @@ circuit top :
           accessor d = m[i]
           d := i
       else :
-        when p2 :
+        wire p3 : UInt(1)
+        when p3 :
           accessor w = m[i] 
           i := w
           accessor x = m[i]
@@ -26,3 +30,4 @@ circuit top :
           i := y
           accessor z = m[i]
           z := i
+; CHECK: Finished Expand Whens
diff --git a/test/passes/initialize-register/begin.fir b/test/passes/initialize-register/begin.fir
deleted file mode 100644
index fab45e64..00000000
--- a/test/passes/initialize-register/begin.fir
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: firrtl %s abcd c | tee %s.out | FileCheck %s 
-
-; CHECK: Initialize Registers
-         circuit top :
-            module top :
-               input a : UInt(16)
-               input b : UInt(16)
-               output z : UInt
-
-               reg r1 : UInt
-; CHECK:       wire [[R1:gen[0-9]*]] : UInt
-; CHECK:       [[R1]] := Null
-
-               reg r2 : UInt
-               r2.init := UInt(0)
-; CHECK-NOT:   r2.init := UInt(0)
-; CHECK:       wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:   r2 := [[R2]]
-; CHECK:       [[R2]] := Null
-; CHECK:       [[R2]] := UInt(0)
-      
-; CHECK:       when reset :
-; CHECK-DAG:      r1 := [[R1]]
-; CHECK-DAG:      r2 := [[R2]]
-
-; CHECK: Finished Initialize Registers
diff --git a/test/passes/initialize-register/when.fir b/test/passes/initialize-register/when.fir
deleted file mode 100644
index 4e0690d8..00000000
--- a/test/passes/initialize-register/when.fir
+++ /dev/null
@@ -1,43 +0,0 @@
-; RUN: firrtl %s abcd c | tee %s.out | FileCheck %s 
-
-; CHECK: Initialize Registers
-         circuit top :
-            module top :
-               input a : UInt(16)
-               input b : UInt(16)
-               output z : UInt
-               when gt(1, 2) :
-                  reg r1: UInt
-                  r1.init := UInt(12)
-; CHECK:          wire [[R1:gen[0-9]*]] : UInt
-; CHECK-NOT:      r1 := [[R1]]
-; CHECK:          [[R1]] := Null
-; CHECK:          [[R1]] := UInt(12)
-; CHECK-NOT:      r1.init := UInt(12)
-                  reg r2: UInt
-; CHECK:          wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:      r2 := [[R2]]
-; CHECK:          [[R2]] := Null
-
-; CHECK:          when reset :
-; CHECK-DAG:         r2 := [[R2]]
-; CHECK-DAG:         r1 := [[R1]]
-               else :
-                  reg r1: UInt
-                  r1.init := UInt(12)
-; CHECK:          wire [[R1:gen[0-9]*]] : UInt
-; CHECK-NOT:      r1 := [[R1]]
-; CHECK:          [[R1]] := Null
-; CHECK:          [[R1]] := UInt(12)
-; CHECK-NOT:      r1.init := UInt(12)
-
-                  reg r2: UInt
-; CHECK:          wire [[R2:gen[0-9]*]] : UInt
-; CHECK-NOT:      r2 := [[R2]]
-; CHECK:          [[R2]] := Null
-
-; CHECK:          when reset :
-; CHECK-DAG:         r2 := [[R2]]
-; CHECK-DAG:         r1 := [[R1]]
-
-; CHECK: Finished Initialize Registers
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
new file mode 100644
index 00000000..9021d0c2
--- /dev/null
+++ b/test/passes/lower-to-ground/register.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl %s abcdefghi c | tee %s.out | FileCheck %s 
+
+; CHECK: Lower To Ground
+         circuit top :
+            module top :
+               input a : UInt(16)
+               input b : UInt(16)
+               output z : UInt
+
+               reg r1 : { x : UInt, flip y : SInt }
+               wire q : { x : UInt, flip y : SInt }
+               r1.init := q    
+
+      ; CHECK: reg r1#x : UInt
+      ; CHECK: reg r1#y : SInt
+      ; CHECK: wire q#x : UInt
+      ; CHECK: wire q#y : SInt
+      ; CHECK: r1#init#x := q#x
+      ; CHECK: q#y := r1#init#y
+
+; CHECK: Finished Lower To Ground