Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.fir doesn't work because incorrecly generated?

16 files changed, 196 insertions, 159 deletions

diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir
index a8857882..b635e4bf 100644
--- a/test/chisel3/LFSR16.fir
+++ b/test/chisel3/LFSR16.fir
@@ -3,12 +3,12 @@
 
 circuit LFSR16 : 
   module LFSR16 : 
-    output out : UInt(16)
-    input inc : UInt(1)
+    output out : UInt<16>
+    input inc : UInt<1>
     
-    node T_16 = UInt(1, 16)
-    reg res : UInt(16)
-    res.init := T_16
+    node T_16 = UInt<16>(1)
+    reg res : UInt<16>
+    on-reset res := T_16
     when inc : 
       node T_17 = bit(res, 0)
       node T_18 = bit(res, 2)
diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir
index a2df4671..e62f35ba 100644
--- a/test/chisel3/MemorySearch.fir
+++ b/test/chisel3/MemorySearch.fir
@@ -2,43 +2,43 @@
 ; CHECK: Done!
 circuit MemorySearch : 
   module MemorySearch : 
-    input target : UInt(4)
-    output address : UInt(3)
-    input en : UInt(1)
-    output odone : UInt(1)
+    input target : UInt<4>
+    output address : UInt<3>
+    input en : UInt<1>
+    output odone : UInt<1>
     
-    node T_35 = UInt(0, 3)
-    reg index : UInt(3)
-    index.init := T_35
-    node T_36 = UInt(0, 1)
-    node T_37 = UInt(4, 3)
-    node T_38 = UInt(15, 4)
-    node T_39 = UInt(14, 4)
-    node T_40 = UInt(2, 2)
-    node T_41 = UInt(5, 3)
-    node T_42 = UInt(13, 4)
-    wire elts : UInt(1)[7]
-    elts.0 := T_36
-    elts.1 := T_37
-    elts.2 := T_38
-    elts.3 := T_39
-    elts.4 := T_40
-    elts.5 := T_41
-    elts.6 := T_42
+    node T_35 = UInt<3>(0)
+    reg index : UInt<3>
+    on-reset index := T_35
+    node T_36 = UInt<1>(0)
+    node T_37 = UInt<3>(4)
+    node T_38 = UInt<4>(15)
+    node T_39 = UInt<4>(14)
+    node T_40 = UInt<2>(2)
+    node T_41 = UInt<3>(5)
+    node T_42 = UInt<4>(13)
+    wire elts : UInt<1>[7]
+    elts[0] := T_36
+    elts[1] := T_37
+    elts[2] := T_38
+    elts[3] := T_39
+    elts[4] := T_40
+    elts[5] := T_41
+    elts[6] := T_42
     accessor elt = elts[index]
     node T_43 = bit-not(en)
     node T_44 = eq(elt, target)
-    node T_45 = UInt(7, 3)
+    node T_45 = UInt<3>(7)
     node T_46 = eq(index, T_45)
     node T_47 = bit-or(T_44, T_46)
     node done = bit-and(T_43, T_47)
     when en : 
-      node T_48 = UInt(0, 1)
+      node T_48 = UInt<1>(0)
       index := T_48
     else : 
       node T_49 = bit-not(done)
       when T_49 : 
-        node T_50 = UInt(1, 1)
+        node T_50 = UInt<1>(1)
         node T_51 = add(index, T_50)
         index := T_51
     odone := done
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index 7198667a..7379024b 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -2,29 +2,29 @@
 ; CHECK: Done!
 circuit ModuleVec : 
   module PlusOne : 
-    input in : UInt(32)
-    output out : UInt(32)
+    input in : UInt<32>
+    output out : UInt<32>
     
-    node T_33 = UInt(1, 1)
+    node T_33 = UInt<1>(1)
     node T_34 = add(in, T_33)
     out := T_34
   module PlusOne_25 : 
-    input in : UInt(32)
-    output out : UInt(32)
+    input in : UInt<32>
+    output out : UInt<32>
     
-    node T_35 = UInt(1, 1)
+    node T_35 = UInt<1>(1)
     node T_36 = add(in, T_35)
     out := T_36
   module ModuleVec : 
-    output ins : UInt(32)[2]
-    output outs : UInt(32)[2]
+    output ins : UInt<32>[2]
+    output outs : UInt<32>[2]
     
     inst T_37 of PlusOne
     inst T_38 of PlusOne_25
-    wire pluses : {flip in : UInt(32), out : UInt(32)}[2]
-    pluses.0 := T_37
-    pluses.1 := T_38
+    wire pluses : {flip in : UInt<32>, out : UInt<32>}[2]
+    pluses[0] := T_37
+    pluses[1] := T_38
     pluses.s.in := ins.s
-    outs.0 := pluses.s.out
-    pluses.s.in := ins.1
-    outs.1 := pluses.1.out
+    outs[0] := pluses.s.out
+    pluses.s.in := ins[1]
+    outs[1] := pluses[1].out
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index 4f954465..1ce6f797 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -2,43 +2,43 @@
 ; CHECK: Done!
 circuit Mul : 
   module Mul : 
-    input y : UInt(2)
-    input x : UInt(2)
-    output z : UInt(4)
+    input y : UInt<2>
+    input x : UInt<2>
+    output z : UInt<4>
     
-    node T_43 = UInt(0, 4)
-    node T_44 = UInt(0, 4)
-    node T_45 = UInt(0, 4)
-    node T_46 = UInt(0, 4)
-    node T_47 = UInt(0, 4)
-    node T_48 = UInt(1, 4)
-    node T_49 = UInt(2, 4)
-    node T_50 = UInt(3, 4)
-    node T_51 = UInt(0, 4)
-    node T_52 = UInt(2, 4)
-    node T_53 = UInt(4, 4)
-    node T_54 = UInt(6, 4)
-    node T_55 = UInt(0, 4)
-    node T_56 = UInt(3, 4)
-    node T_57 = UInt(6, 4)
-    node T_58 = UInt(9, 4)
-    wire tbl : UInt(4)[16]
-    tbl.0 := T_43
-    tbl.1 := T_44
-    tbl.2 := T_45
-    tbl.3 := T_46
-    tbl.4 := T_47
-    tbl.5 := T_48
-    tbl.6 := T_49
-    tbl.7 := T_50
-    tbl.8 := T_51
-    tbl.9 := T_52
-    tbl.10 := T_53
-    tbl.11 := T_54
-    tbl.12 := T_55
-    tbl.13 := T_56
-    tbl.14 := T_57
-    tbl.15 := T_58
+    node T_43 = UInt<4>(0)
+    node T_44 = UInt<4>(0)
+    node T_45 = UInt<4>(0)
+    node T_46 = UInt<4>(0)
+    node T_47 = UInt<4>(0)
+    node T_48 = UInt<4>(1)
+    node T_49 = UInt<4>(2)
+    node T_50 = UInt<4>(3)
+    node T_51 = UInt<4>(0)
+    node T_52 = UInt<4>(2)
+    node T_53 = UInt<4>(4)
+    node T_54 = UInt<4>(6)
+    node T_55 = UInt<4>(0)
+    node T_56 = UInt<4>(3)
+    node T_57 = UInt<4>(6)
+    node T_58 = UInt<4>(9)
+    wire tbl : UInt<4>[16]
+    tbl[0] := T_43
+    tbl[1] := T_44
+    tbl[2] := T_45
+    tbl[3] := T_46
+    tbl[4] := T_47
+    tbl[5] := T_48
+    tbl[6] := T_49
+    tbl[7] := T_50
+    tbl[8] := T_51
+    tbl[9] := T_52
+    tbl[10] := T_53
+    tbl[11] := T_54
+    tbl[12] := T_55
+    tbl[13] := T_56
+    tbl[14] := T_57
+    tbl[15] := T_58
     node T_60 = shl(x, 2)
     node T_61 = bit-or(T_60, y)
     accessor T_62 = tbl[T_61]
diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir
index 227c5dae..2e1e4475 100644
--- a/test/chisel3/Outer.fir
+++ b/test/chisel3/Outer.fir
@@ -2,18 +2,18 @@
 ; CHECK: Done!
 circuit Outer : 
   module Inner : 
-    input in : UInt(8)
-    output out : UInt(8)
+    input in : UInt<8>
+    output out : UInt<8>
     
-    node T_14 = UInt(1, 1)
+    node T_14 = UInt<1>(1)
     node T_15 = add(in, T_14)
     out := T_15
   module Outer : 
-    input in : UInt(8)
-    output out : UInt(8)
+    input in : UInt<8>
+    output out : UInt<8>
     
     inst T_16 of Inner
     T_16.in := in
-    node T_17 = UInt(2, 2)
+    node T_17 = UInt<2>(2)
     node T_18 = mul(T_16.out, T_17)
     out := T_18
diff --git a/test/chisel3/RegisterVecShift.fir b/test/chisel3/RegisterVecShift.fir
index 7fae4c49..5a184366 100644
--- a/test/chisel3/RegisterVecShift.fir
+++ b/test/chisel3/RegisterVecShift.fir
@@ -2,35 +2,35 @@
 ; CHECK: Done!
 circuit RegisterVecShift : 
   module RegisterVecShift : 
-    input load : UInt(1)
-    output out : UInt(4)
-    input shift : UInt(1)
-    input ins : UInt(4)[4]
+    input load : UInt<1>
+    output out : UInt<4>
+    input shift : UInt<1>
+    input ins : UInt<4>[4]
     
-    reg delays : UInt(4)[4]
+    reg delays : UInt<4>[4]
     when reset : 
-      node T_39 = UInt(0, 4)
-      node T_40 = UInt(0, 4)
-      node T_41 = UInt(0, 4)
-      node T_42 = UInt(0, 4)
-      wire T_43 : UInt(4)[4]
-      T_43.0 := T_39
-      T_43.1 := T_40
-      T_43.2 := T_41
-      T_43.3 := T_42
+      node T_39 = UInt<4>(0)
+      node T_40 = UInt<4>(0)
+      node T_41 = UInt<4>(0)
+      node T_42 = UInt<4>(0)
+      wire T_43 : UInt<4>[4]
+      T_43[0] := T_39
+      T_43[1] := T_40
+      T_43[2] := T_41
+      T_43[3] := T_42
       delays := T_43
-    node T_44 = UInt(5, 3)
+    node T_44 = UInt<3>(5)
     node T_45 = bit-and(T_44, load)
-    node T_46 = UInt(4, 3)
+    node T_46 = UInt<3>(4)
     node T_47 = eq(T_45, T_46)
     when T_47 : 
-      delays.0 := ins.0
-      delays.1 := ins.1
-      delays.2 := ins.2
-      delays.3 := ins.3
+      delays[0] := ins[0]
+      delays[1] := ins[1]
+      delays[2] := ins[2]
+      delays[3] := ins[3]
      else : when shift : 
-        delays.0 := ins.0
-        delays.1 := delays.0
-        delays.2 := delays.1
-        delays.3 := delays.2
-    out := delays.3
+        delays[0] := ins[0]
+        delays[1] := delays[0]
+        delays[2] := delays[1]
+        delays[3] := delays[2]
+    out := delays[3]
diff --git a/test/chisel3/Stack.fir b/test/chisel3/Stack.fir
index fbd198eb..a6f33189 100644
--- a/test/chisel3/Stack.fir
+++ b/test/chisel3/Stack.fir
@@ -2,41 +2,41 @@
 ; CHECK: Done!
 circuit Stack : 
   module Stack : 
-    input push : UInt(1)
-    input pop : UInt(1)
-    input en : UInt(1)
-    output dataOut : UInt(32)
-    input dataIn : UInt(32)
+    input push : UInt<1>
+    input pop : UInt<1>
+    input en : UInt<1>
+    output dataOut : UInt<32>
+    input dataIn : UInt<32>
     
-    mem stack_mem : UInt(32)[16]
-    node T_30 = UInt(0, 5)
-    reg sp : UInt(5)
-    sp.init := T_30
-    node T_31 = UInt(0, 32)
-    reg out : UInt(32)
-    out.init := T_31
+    mem stack_mem : UInt<32>[16]
+    node T_30 = UInt<5>(0)
+    reg sp : UInt<5>
+    on-reset sp := T_30
+    node T_31 = UInt<32>(0)
+    reg out : UInt<32>
+    on-reset out := T_31
     when en : 
-      node T_32 = UInt(16, 5)
+      node T_32 = UInt<5>(16)
       node T_33 = lt(sp, T_32)
       node T_34 = bit-and(push, T_33)
       when T_34 : 
         accessor T_35 = stack_mem[sp]
         T_35 := dataIn
-        node T_36 = UInt(1, 1)
+        node T_36 = UInt<1>(1)
         node T_37 = add-wrap(sp, T_36)
         sp := T_37
       else : 
-        node T_38 = UInt(0, 1)
+        node T_38 = UInt<1>(0)
         node T_39 = gt(sp, T_38)
         node T_40 = bit-and(pop, T_39)
         when T_40 : 
-          node T_41 = UInt(1, 1)
+          node T_41 = UInt<1>(1)
           node T_42 = sub-wrap(sp, T_41)
           sp := T_42
-      node T_43 = UInt(0, 1)
+      node T_43 = UInt<1>(0)
       node T_44 = gt(sp, T_43)
       when T_44 : 
-        node T_45 = UInt(1, 1)
+        node T_45 = UInt<1>(1)
         node T_46 = sub-wrap(sp, T_45)
         accessor T_47 = stack_mem[T_46]
         out := T_47
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 0b6b19fa..6e3109a5 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -22,14 +22,14 @@ circuit top :
       when gt(x, y) :
       ;CHECK: when gt-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>
+         ;CHECK: inst s of subtracter@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>
          s.x := x
          s.y := y
          x := s.z
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.reset@<t:UInt> := reset@<t:UInt>
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
-         ;CHECK: x@<t:UInt> := s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.z@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.reset@<t:UInt> := reset@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
+         ;CHECK: x@<t:UInt> := s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.z@<t:UInt>      
       else :
          inst s2 of subtracter
          s2.x := x
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index 3cd5c542..435540ae 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p ctd | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Widths
 circuit top :
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 2b73a8e9..f15980b3 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
 circuit top :
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index ca676ba5..722d569c 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s
 
 circuit top :
    module m :
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
new file mode 100644
index 00000000..4cd9f0cc
--- /dev/null
+++ b/test/passes/lower-to-ground/instance.fir
@@ -0,0 +1,35 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cdg | tee %s.out | FileCheck %s
+
+circuit top :
+   module source :
+      output data : UInt<16>
+      input ready : UInt<1>
+      data := UInt(16)
+   module sink :
+      input data : UInt<16>
+      output ready : UInt<1>
+   module top: 
+      wire connect : { data : UInt<16>, flip ready: UInt<1> }
+      wire connect2 : { flip data : UInt<16>, ready: UInt<1> }
+      inst src of source         
+      inst snk of sink           
+      connect := src   
+      connect2 := snk
+
+
+; CHECK: Resolve Genders
+
+; CHECK: connect@<g:f> := src@<g:m>
+; CHECK: connect2@<g:f> := snk@<g:m>
+
+; CHECK: Finished Resolve Genders
+
+
+; CHECK: Lower To Ground
+
+; CHECK: connect$data@<g:f> := src@<g:m>.data@<g:m>
+; CHECK: src@<g:m>.ready@<g:f> := connect$ready@<g:m>
+; CHECK: snk@<g:m>.data@<g:f> := connect2$data@<g:m>
+; CHECK: connect2$ready@<g:f> := snk@<g:m>.ready@<g:m>
+
+; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index 1e9c8f9f..95b125f6 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -5,6 +5,7 @@ circuit top :
    module q :
       wire i : UInt
       wire j : { x : UInt<32>, flip y : UInt<32> }
+      wire k : { x : UInt<32>, y : UInt<32> }
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
       ; CHECK: wire a$0$x : UInt<32>
@@ -19,16 +20,17 @@ circuit top :
       ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
 
-      mem m : { x : UInt<32>, flip y : UInt<32> }[2]
+      mem m : { x : UInt<32>, y : UInt<32> }[2]
       ; CHECK: mem m$x : UInt<32>[2]
       ; CHECK: mem m$y : UInt<32>[2]
 
       accessor c = m[i] ; MALE
       ; CHECK: accessor c$x = m$x[i]
       ; CHECK: accessor c$y = m$y[i]
-      ; CHECK: c$x := j$x
-      ; CHECK: j$y := c$y
-      c := j
+
+      c := k
+      ; CHECK: c$x := k$x
+      ; CHECK: c$y := k$y
 
 ; CHECK: Finished Lower To Ground
 
diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
index 8cae8ba4..caf7d4b3 100644
--- a/test/passes/resolve-genders/accessor.fir
+++ b/test/passes/resolve-genders/accessor.fir
@@ -5,15 +5,15 @@ circuit top :
    module top :
       wire m : UInt<32>[10][10][10]
       wire i : UInt
-      accessor a = m[i] ;CHECK: accessor a = m@<g:male>[i@<g:male>]@<g:male>
-      accessor b = a[i] ;CHECK: accessor b = a@<g:male>[i@<g:male>]@<g:male>
-      accessor c = b[i] ;CHECK: accessor c = b@<g:male>[i@<g:male>]@<g:male>
+      accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m>
+      accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m>
+      accessor c = b[i] ;CHECK: accessor c = b@<g:m>[i@<g:m>]@<g:m>
       wire j : UInt
       j := c
 
-      accessor x = m[i] ;CHECK: accessor x = m@<g:female>[i@<g:male>]@<g:female>
-      accessor y = x[i] ;CHECK: accessor y = x@<g:female>[i@<g:male>]@<g:female>
-      accessor z = y[i] ;CHECK: accessor z = y@<g:female>[i@<g:male>]@<g:female>
+      accessor x = m[i] ;CHECK: accessor x = m@<g:f>[i@<g:m>]@<g:f>
+      accessor y = x[i] ;CHECK: accessor y = x@<g:f>[i@<g:m>]@<g:f>
+      accessor z = y[i] ;CHECK: accessor z = y@<g:f>[i@<g:m>]@<g:f>
       z := j
 
 ; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index b16c9b66..2f7aae73 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -7,7 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-wrap(x, y)
-      ;CHECK: z@<g:female> := sub-wrap-uu(x@<g:male>, y@<g:male>)
+      ;CHECK: z@<g:f> := sub-wrap-uu(x@<g:m>, y@<g:m>)
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
@@ -20,15 +20,15 @@ circuit top :
       on-reset x := UInt(0)
       on-reset y := UInt(42)
       when gt(x, y) :
-      ;CHECK: when gt-uu(x@<g:male>, y@<g:male>) :
+      ;CHECK: when gt-uu(x@<g:m>, y@<g:m>) :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<g:female>
+         ;CHECK: inst s of subtracter@<g:m>
          s.x := x
          s.y := y
          x := s.z
-         ;CHECK: s@<g:female>.x@<g:female> := x@<g:male>
-         ;CHECK: s@<g:female>.y@<g:female> := y@<g:male>
-         ;CHECK: x@<g:female> := s@<g:female>.z@<g:male>
+         ;CHECK: s@<g:m>.x@<g:f> := x@<g:m>
+         ;CHECK: s@<g:m>.y@<g:f> := y@<g:m>
+         ;CHECK: x@<g:f> := s@<g:m>.z@<g:m>
       else :
          inst s2 of subtracter
          s2.x := x
diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir
index 3155dbcf..9bc67c21 100644
--- a/test/passes/resolve-genders/ports.fir
+++ b/test/passes/resolve-genders/ports.fir
@@ -11,11 +11,11 @@ circuit top :
       output ready : UInt<1>
    module top: 
       wire connect : { data : UInt<16>, flip ready: UInt<1> }
-      inst src of source         ;CHECK: inst src of source@<g:female>
-      inst snk of sink           ;CHECK: inst snk of sink@<g:female>
-      connect.data := src.data   ;CHECK: connect@<g:female>.data@<g:female> := src@<g:female>.data@<g:male>
-      src.ready := connect.ready ;CHECK: src@<g:female>.ready@<g:female> := connect@<g:female>.ready@<g:male>
-      snk.data := connect.data   ;CHECK: snk@<g:female>.data@<g:female> := connect@<g:male>.data@<g:male>
-      connect.ready := snk.ready ;CHECK: connect@<g:male>.ready@<g:female> := snk@<g:female>.ready@<g:male>
+      inst src of source         ;CHECK: inst src of source@<g:m>
+      inst snk of sink           ;CHECK: inst snk of sink@<g:m>
+      connect.data := src.data   ;CHECK: connect@<g:f>.data@<g:f> := src@<g:m>.data@<g:m>
+      src.ready := connect.ready ;CHECK: src@<g:m>.ready@<g:f> := connect@<g:f>.ready@<g:m>
+      snk.data := connect.data   ;CHECK: snk@<g:m>.data@<g:f> := connect@<g:m>.data@<g:m>
+      connect.ready := snk.ready ;CHECK: connect@<g:m>.ready@<g:f> := snk@<g:m>.ready@<g:m>
 
 ; CHECK: Finished Resolve Genders