Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.fir doesn't work because incorrecly generated?

18 files changed, 377 insertions, 414 deletions

diff --git a/TODO b/TODO
index fd5685bd..1c84cc96 100644
--- a/TODO
+++ b/TODO
@@ -5,8 +5,9 @@
 ======== Current Tasks ========
 Make instances always male, flip the bundles on declaration
 dlsh,drsh
-move Infer-Widths to before vec expansion?
 Add Unit Tests for each pass
+<>
+Update spec
    
 ======== Update Core ==========
 Add source locaters
@@ -26,6 +27,8 @@ Well-formed high firrtl
    onreset can only handle a register
    all references are declared
    expression in pad must be a ground type
+   node's value cannot be a bundle with a flip in it
+   mems cannot be a bundle with flips
 After adding dynamic assertions, insert bounds check with accessor expansion
 Well-formed low firrtl
    All things only assigned to once
@@ -53,6 +56,7 @@ Patrick:
    move Infer-Widths to before vec expansion?
 
 ======== Think About ========
+<>
 subword accesses
 verilog style guide
 naming for split nodes
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index dacdce36..31d8fc5f 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -117,8 +117,8 @@ defn times (f1:Flip,f2:Flip) -> Flip :
       REVERSE : swap(f1)
      
 defn to-field (p:Port) -> Field :
-   if direction(p) == OUTPUT : Field(name(p),REVERSE,type(p))
-   else if direction(p) == INPUT : Field(name(p),DEFAULT,type(p))
+   if direction(p) == OUTPUT : Field(name(p),DEFAULT,type(p))
+   else if direction(p) == INPUT : Field(name(p),REVERSE,type(p))
    else : error("Shouldn't be here")
 
 defn to-dir (g:Gender) -> Direction :
@@ -128,15 +128,15 @@ defn to-dir (g:Gender) -> Direction :
 
 defmulti gender (e:Expression) -> Gender
 defmethod gender (e:Expression) :
-   MALE ; TODO, why was this OUTPUT before? It makes sense as male, not female
+   MALE
 
 defmethod print (o:OutputStream, g:Gender) :
    print{o, _} $
    switch {g == _} :
-      MALE : "male"
-      FEMALE: "female"
-      BI-GENDER : "bi"
-      UNKNOWN-GENDER: "unknown"
+      MALE : "m"
+      FEMALE: "f"
+      BI-GENDER : "b"
+      UNKNOWN-GENDER: "u"
 
 defmethod type (exp:UIntValue) -> Type : UIntType(width(exp))
 defmethod type (exp:SIntValue) -> Type : SIntType(width(exp))
@@ -496,8 +496,7 @@ defn infer-types (c:Circuit) -> Circuit :
 defn bundle-field-flip (n:Symbol,t:Type) -> Flip :
    match(t) :
       (b:BundleType) : 
-          val field = for f in fields(b) find :
-                         name(f) == n
+          val field = for f in fields(b) find : name(f) == n
           match(field):
                    (f:Field) : flip(f)
                    (f) : error(string-join(["Could not find " n " in bundle "]))
@@ -541,8 +540,8 @@ defn resolve-genders (c:Circuit) :
             (s:DefNode) : 
                DefNode(name(s),resolve-expr(value(s),get-gender(name(s),MALE)))
             (s:DefInstance) :
-               get-gender(name(s),FEMALE)
-               DefInstance(name(s),resolve-expr(module(s),FEMALE))
+               get-gender(name(s),MALE)
+               DefInstance(name(s),resolve-expr(module(s),MALE))
             (s:WDefAccessor) : 
                val gender* = get-gender(name(s),UNKNOWN-GENDER)
                val index* = resolve-expr(index(s),MALE)
@@ -642,6 +641,21 @@ defn expand-accessors (c:Circuit) :
 ;   to the lowered ground expression names and genders. This allows
 ;   references to be resolved.
 
+defstruct EF :
+   exp : Expression
+   flip : Flip
+
+defmethod print (o:OutputStream,e:EF) :
+   print-all(o, ["EF(" exp(e) "," flip(e) ")"])
+   
+defmethod print (o:OutputStream,e:NTF) :
+   print-all(o, ["NTF(" name(e) "," type(e) "," flip(e) ")"])
+
+defstruct NTF :
+   name : Symbol
+   type : Type
+   flip : Flip
+
 defn num-elems (t:Type) -> Int :
    match(t) :
       (t:BundleType) : 
@@ -660,194 +674,182 @@ defn index-of-elem (t:BundleType, s:Symbol) -> Int :
          else : sum = sum + num-elems(type(f))
       error("Shouldn't be here")
 
-defn lower-ports (m:Module, table:HashTable<Symbol,List<KeyValue<Expression,Flip>>>) -> List<Port> :
-   val entries = table[name(m)]
-   val directions = 
-      for p in ports(m) map-append :
-         to-list(for i in 0 to num-elems(type(p)) stream : direction(p))
-   for (kv in entries, d in directions) map :
-      val exp = key(kv) as WRef
-      val dir* = d * value(kv)
-      Port(name(exp),dir*,type(exp))
-
-defn lower (body:Stmt, table:HashTable<Symbol,List<KeyValue<Expression,Flip>>>) -> Stmt :
+
+defn generate-entry (n:Symbol,t:Type) -> List<NTF> :
+   defn uniquify (n*:Symbol) -> Symbol : symbol-join([n "$" n*])
+   match(t) :
+      (t:BundleType) : 
+         for f in fields(t) map-append :
+            val es = generate-entry(name(f),type(f))
+            for e in es map :
+               NTF(uniquify(name(e)),type(e),flip(e) * flip(f))
+      (t:VectorType) :
+         for i in 0 to size(t) map-append :
+            val es = generate-entry(to-symbol(i),type(t))
+            for e in es map :
+               NTF(uniquify(name(e)),type(e),flip(e))
+      (t) : list $ NTF(n,t,DEFAULT)
+
+defn expand-expr (e:Expression) -> List<EF> :
+   defn inst? (e:Expression) -> True|False :
+      match(e) :
+         (e:WRef) : kind(e) == InstanceKind()
+         (e) : false
+   match(e) :
+      (e:WRef) : 
+         if inst?(e) : 
+            for f in fields(type(e) as BundleType) map-append :
+               for x in generate-entry(name(f),type(f)) map :
+                  EF(WSubfield(e,name(x),type(x),gender(e)),flip(f) * flip(x))
+         else :
+            for x in generate-entry(name(e),type(e)) map :
+               EF(WRef(name(x),type(x),kind(e),gender(e)), flip(x))
+      (e:WSubfield) : 
+         if inst?(exp(e)) : 
+            val i = exp(e)
+            val f = {_ as Field} $
+               for f in fields(type(i) as BundleType) find : name(f) == name(e)
+            for x in generate-entry(name(f),type(f)) map :
+               EF(WSubfield(i,name(x),type(x),gender(e)),flip(x))
+         else :
+            val b = exp(e)
+            val exps = for x in generate-entry(name(b as WRef),type(b)) map :
+               EF(WRef(name(x),type(x),NodeKind(),gender(e)),DEFAULT)
+            val begin = index-of-elem(type(b) as BundleType,name(e))
+            val len = num-elems(type(e))
+            headn(tailn(exps,begin),len)
+      (e:WIndex) :
+         val exps = expand-expr(exp(e))
+         val len = num-elems(type(e))
+         headn(tailn(exps,len * value(e)),len)
+      (e:Pad) : 
+         val v = exp(head(expand-expr(value(e))))
+         list(EF(Pad(v,width(e),type(e)),DEFAULT))
+      (e:DoPrim) :
+         val args = for x in args(e) map : exp(head(expand-expr(x)))
+         list(EF(DoPrim(op(e),args,consts(e),type(e)),DEFAULT))
+      (e) : list(EF(e,DEFAULT))
+
+defn lower-ports (ports:List<Port>) -> List<Port> :
+   for p in ports map-append :
+      for x in generate-entry(name(p),type(p)) map :
+         Port(name(x),direction(p) * flip(x),type(x))
+
+defn type (s:WDefAccessor) -> Type : type(type(source(s)) as VectorType)
+defn size (s:DefMemory) -> Int : size(type(s))
+defn size (s:WDefAccessor) -> Int : size(type(source(s)) as VectorType)
+defn kind (e:WSubfield) -> Kind : kind(exp(e) as WRef|WSubfield|WIndex)
+defn kind (e:WIndex) -> Kind : kind(exp(e) as WRef|WSubfield|WIndex)
+
+defn set-gender (e:Expression,g:Gender,f:Flip) -> Expression :
+   match(e) : 
+      (e:WRef) : WRef(name(e),type(e),kind(e),g)
+      (e:WSubfield) : WSubfield(set-gender(exp(e),g * f,DEFAULT),name(e),type(e),g)
+      (e) : e
+
+defn lower (body:Stmt) -> Stmt :
    defn lower-stmt (s:Stmt) -> Stmt :
-      defn add-to-table (y:Symbol,k:KeyValue<Expression,Flip>,ctable:HashTable<Symbol,List<KeyValue<Expression,Flip>>>) :
-         val contains? = for x in ctable any? :
-                            key(x) == y
-         if contains? : ctable[y] = append(ctable[y],list(k))
-         else : ctable[y] = list(k)
-      defn is-instance (e:Expression) -> True|False :
-         match(e) :
-            (e:WRef) : kind(e) == InstanceKind()
-            (e) : false
       defn calc-gender (g:Gender, e:Expression) -> Gender :
          match(e) :
             (e:WRef) : gender(e)
             (e:WSubfield) : 
-               if is-instance(exp(e)) : gender(e)
-               else : calc-gender(bundle-field-flip(name(e),type(exp(e))) * g,exp(e))
+               println-all-debug(["Calc gender. " g " with " e])
+               println-all-debug(["Exp: " exp(e)])
+               val flip = bundle-field-flip(name(e),type(exp(e)))
+               println-all-debug(["Flip: " flip])
+               calc-gender(flip * g,exp(e))
             (e:WIndex) : gender(e)
             (e) : g
 
+      println(s)
       match(s) :
-         (s:DefWire) : Begin{_} $
-            for t in table[name(s)] map :
-               DefWire(name(key(t) as WRef),type(key(t)))
+         (s:DefWire) : Begin $
+            for x in generate-entry(name(s),type(s)) map :
+               DefWire(name(x),type(x))
          (s:DefRegister) : Begin{_} $
-            for t in table[name(s)] map :
-               DefRegister(name(key(t) as WRef),type(key(t)))
+            for x in generate-entry(name(s),type(s)) map :
+               DefRegister(name(x),type(x))
          (s:DefInstance) : s
-         (s:DefNode) :
-            val s* = Begin $ list(
-               DefWire(name(s),type(value(s))),
-               Connect(WRef(name(s),type(value(s)),NodeKind(),FEMALE),value(s)))
-            lower-stmt(s*)
-         (s:OnReset) : Begin{_} $
+         (s:DefNode) : Begin $
+            for x in expand-expr(value(s)) map : 
+               DefNode(name(s),exp(x))
+         (s:DefMemory) : Begin $ 
+            for x in generate-entry(name(s),type(type(s))) map :
+               DefMemory(name(x),VectorType(type(x),size(s)))
+         (s:WDefAccessor) : 
+            val ls = generate-entry(name(s),type(s))
+            val rs = generate-entry(name(source(s) as WRef),type(s))
+            Begin $ for (l in ls, r in rs) map:
+               if flip(r) == REVERSE : error("Shouldn't be here")
+               val memref = WRef(name(r),VectorType(type(r),size(s)),MemKind(),gender(s))
+               WDefAccessor(name(l),memref,index(s),gender(s))
+         (s:OnReset|Connect) : Begin $
             for (l in expand-expr(loc(s)), r in expand-expr(exp(s))) map :
-               println-debug(s)
-               val lgender = calc-gender(FEMALE,loc(s)) * value(l)
-               val rgender = calc-gender(MALE,exp(s)) * value(r)
-               println-debug(loc(s))
-               println-debug(exp(s))
+               val lgender = FEMALE * flip(l)
+               val rgender = MALE * flip(r)
+               val l* = set-gender(exp(l),lgender,flip(l))
+               val r* = set-gender(exp(r),rgender,flip(r))
+               println-all-debug(["Left: " l " with Gender: " lgender])
+               println-all-debug(["Right: " r " with Gender: " rgender])
                switch fn ([x,y]) : lgender == x and rgender == y :
-                  [FEMALE,MALE]   : OnReset(key(l),key(r))
-                  [MALE,FEMALE]   : OnReset(key(r),key(l))
-         (s:Connect) : Begin{_} $
-            for (l in expand-expr(loc(s)), r in expand-expr(exp(s))) map :
-               println-debug(s)
-               val lgender = calc-gender(FEMALE,loc(s)) * value(l)
-               val rgender = calc-gender(MALE,exp(s)) * value(r)
-               println-debug(loc(s))
-               println-debug(exp(s))
-               switch fn ([x,y]) : lgender == x and rgender == y :
-                  [FEMALE,MALE]   : Connect(key(l),key(r))
-                  [MALE,FEMALE]   : Connect(key(r),key(l))
-         (s:WDefAccessor) : Begin{_} $
-            for (l in table[name(s)], r in expand-expr(source(s))) map:
-               WDefAccessor(name(key(l) as WRef),key(r),index(s),value(r) * gender(s))
+                  [FEMALE,MALE]  : 
+                     if s typeof Connect : Connect(l*,r*)
+                     else : OnReset(l*,r*)
+                  [MALE,FEMALE]  : 
+                     if s typeof Connect : Connect(r*,l*)
+                     else : OnReset(r*,l*)
          (s:ConnectFromIndexed) : Begin(ls) where :
-            val ctable = HashTable<Symbol,List<KeyValue<Expression,Flip>>>(symbol-hash)
+            val ctable = HashTable<Symbol,Vector<EF>>(symbol-hash)
             for e in exps(s) do :
                for (r in expand-expr(e),l in expand-expr(loc(s))) do :
-                  add-to-table(name(key(l) as WRef),r,ctable)
-            val ls = 
-               for l in expand-expr(loc(s)) map :
-                  val cg = calc-gender(FEMALE,loc(s))
-                  val lgender = cg * value(l)
-                  var rgender = BI-GENDER
-                  val exps = for e in ctable[name(key(l) as WRef)] map :
-                                rgender = rgender + (swap(cg) * value(e))
-                                key(e)
+                  val n = name(exp(l) as WRef)
+                  val x = get?(ctable,n,Vector<EF>())
+                  add(x,r)
+                  ctable[n] = x
+            val ls = for l in expand-expr(loc(s)) map :
+                  val n = name(exp(l) as WRef)
+                  val lgender = FEMALE * flip(l)
+                  for x in ctable[n] do : 
+                     if (flip(x) * MALE) == lgender : error("Shouldn't be here")
+                  val rgender = lgender * REVERSE
+                  val l* = set-gender(exp(l),lgender,flip(l))
+                  val exps = to-list $ for e in ctable[n] map : set-gender(exp(e),rgender,flip(e))
                   switch fn ([x,y]) : lgender == x and rgender == y :
-                     [FEMALE,MALE]   : ConnectFromIndexed(index(s),key(l),exps)
-                     [MALE,FEMALE]   : ConnectToIndexed(index(s),exps,key(l))
+                     [FEMALE,MALE]   : ConnectFromIndexed(index(s),l*,exps)
+                     [MALE,FEMALE]   : ConnectToIndexed(index(s),exps,l*)
          (s:ConnectToIndexed) : Begin(ls) where :
-            val ctable = HashTable<Symbol,List<KeyValue<Expression,Flip>>>(symbol-hash)
-            for ls in locs(s) do :
-               for (l in expand-expr(ls),r in expand-expr(exp(s))) do :
-                  add-to-table(name(key(r) as WRef),l,ctable)
-            val ls = 
-               for r in expand-expr(exp(s)) map :
-                  val n = name(key(r) as WRef)
-                  val cg = calc-gender(MALE,exp(s))
-                  val rgender = cg * value(r)
-                  var lgender = BI-GENDER
-                  val locs = for l in ctable[n] map :
-                                lgender = lgender + (swap(cg) * value(l))
-                                key(l)
+            val ctable = HashTable<Symbol,Vector<EF>>(symbol-hash)
+            for e in locs(s) do :
+               for (l in expand-expr(e),r in expand-expr(exp(s))) do :
+                  val n = name(exp(r) as WRef)
+                  val x = get?(ctable,n,Vector<EF>())
+                  add(x,l)
+                  ctable[n] = x
+            val ls = for r in expand-expr(exp(s)) map :
+                  val n = name(exp(r) as WRef)
+                  val rgender = MALE * flip(r)
+                  for x in ctable[n] do : 
+                     if (flip(x) * FEMALE) == rgender : error("Shouldn't be here")
+                  val lgender = rgender * REVERSE
+                  val r* = set-gender(exp(r),rgender,flip(r))
+                  val locs = to-list $ for e in ctable[n] map : set-gender(exp(e),lgender,flip(e))
                   switch fn ([x,y]) : lgender == x and rgender == y :
-                     [FEMALE,MALE]   : ConnectToIndexed(index(s),locs,key(r))
-                     [MALE,FEMALE]   : ConnectFromIndexed(index(s),key(r),locs)
-         (s:DefMemory) : Begin{_} $ 
-            for t in table[name(s)] map :
-               DefMemory(name(key(t) as WRef),type(key(t)) as VectorType)
-         (s) : map(lower-stmt,s)
-
-   defn expand-expr (e:Expression) -> List<KeyValue<Expression,Flip>> :
-      match(e) :
-         (e:WRef) : table[name(e)]
-         (e:WSubfield) : 
-            val exps = expand-expr(exp(e))
-            val begin = index-of-elem(type(exp(e)) as BundleType,name(e))
-            val len = num-elems(type(e))
-            headn(tailn(exps,begin),len)
-         (e:WIndex) :
-            val exps = expand-expr(exp(e))
-            val len = num-elems(type(e))
-            headn(tailn(exps,len * value(e)),len)
-         (e:Pad) : 
-            val v = key(expand-expr(value(e))[0])
-            list(KeyValue(Pad(v,width(e),type(e)),DEFAULT))
-         (e:DoPrim) :
-            val args = for x in args(e) map : key(expand-expr(x)[0])
-            list(KeyValue(DoPrim(op(e),args,consts(e),type(e)),DEFAULT))
-         (e) : list(KeyValue(e, DEFAULT))
-
-   ;println-debug(table)
+                     [FEMALE,MALE]   : ConnectToIndexed(index(s),locs,r*)
+                     [MALE,FEMALE]   : ConnectFromIndexed(index(s),r*,locs)
+         (s:Begin|Conditionally|EmptyStmt) : map(lower-stmt,s)
+
    lower-stmt(body)
 
-defn get-entries (n:Symbol,t:Type) -> List<KeyValue<WRef,Flip>> :
-   defn uniquify (w:WRef) -> WRef :
-      val name* = symbol-join([n "$" name(w)])
-      WRef(name*,type(w),kind(w),gender(w))
-   match(t) :
-      (t:BundleType) : 
-         for f in fields(t) map-append :
-            val es = get-entries(name(f),type(f))
-            for e in es map :
-               uniquify(key(e)) => value(e) * flip(f)
-      (t:VectorType) :
-         for i in 0 to size(t) map-append :
-            val es = get-entries(to-symbol(i),type(t))
-            for e in es map :
-               uniquify(key(e)) => value(e)
-      (t) : list(KeyValue(WRef(n,t,NodeKind(),UNKNOWN-GENDER),DEFAULT))
-
-defn lower-module (m:Module,table:HashTable<Symbol,List<KeyValue<Expression,Flip>>>) -> Module :
-   defn build-table-ports (ports:List<Port>) :
-      for p in ports do :
-         table[name(p)] = get-entries(name(p),type(p))
-
-   defn build-table-stmt (stmt:Stmt) -> Stmt:
-      match(stmt) :
-         (s:DefWire) : table[name(s)] = get-entries(name(s),type(s))
-         (s:DefRegister) : 
-            val regs = get-entries(name(s),type(s))
-            table[name(s)] = regs
-         (s:DefInstance) : 
-            val r = WRef(name(s),type(module(s)),InstanceKind(),FEMALE)
-            val ports = table[name(module(s) as WRef)]
-            table[name(s)] =
-               for w in ports map-append :
-                  list(KeyValue(WSubfield(r,name(key(w) as WRef),type(key(w) as WRef),UNKNOWN-GENDER), value(w)))
-         (s:DefMemory) : table[name(s)] = 
-            for x in get-entries(name(s),type(type(s) as VectorType)) map :
-               val [w f] = [key(x) value(x)]
-               WRef(name(w),VectorType(type(w),size(type(s) as VectorType)),kind(w),gender(w)) => f
-         (s:DefNode) : table[name(s)] = get-entries(name(s),type(value(s)))
-         (s:WDefAccessor) : table[name(s)] = get-entries(name(s),type(type(source(s)) as VectorType))
-         (s) : map(build-table-stmt,s)
-      stmt
-
-   build-table-ports(ports(m))
-   build-table-stmt(body(m)) 
+defn lower-module (c:Circuit,m:Module) -> Module : 
    Module(name(m),ports*,body*) where :
-      val body* = lower(body(m),table)
-      val ports* = lower-ports(m,table)
+      val body* = lower(body(m))
+      val ports* = lower-ports(ports(m))
 
 defn lower-to-ground (c:Circuit) -> Circuit :
-   val table = HashTable<Symbol,List<KeyValue<Expression,Flip>>>(symbol-hash)
-   defn build-table-module (m:Module) -> ? :
-      table[name(m)] = for p in ports(m) map-append : get-entries(name(p),type(p))
-
-   for m in modules(c) map :
-      build-table-module(m)
-
    Circuit(modules*, main(c)) where :
       val modules* = 
          for m in modules(c) map :
-            lower-module(m,table)
+            lower-module(c,m)
 
 
 ;;=========== CONVERT MULTI CONNECTS to WHEN ================
@@ -888,83 +890,6 @@ defn expand-connect-indexed (c: Circuit) -> Circuit :
         for m in modules(c) map :
            expand-connect-indexed(m)
 
-;======= MAKE EXPLICIT REGISTER INITIALIZATION =============
-; This pass replaces the reg.init construct by creating a new
-;   wire that holds the value at initialization. This wire
-;   is then connected to the register conditionally on reset,
-;   at the end of the scope containing the  register 
-;   declaration
-; If a register has no inital value, the wire is connected to
-;   a NULL node. Later passes will remove these with the base
-;   case Mux(reset,NULL,a) -> a, and Mux(reset,a,NULL) -> a.
-;   This ensures proper behavior if this pass is run multiple 
-;   times.
-
-;defn initialize-registers (c:Circuit) :
-;   defn to-wire-name (y:Symbol) : symbol-join([ y "$init"])
-;   defn add-when (s:Stmt,h:HashTable<Symbol,Type>) -> Stmt :
-;      var inits = List<Stmt>()
-;      for kv in h do :
-;         val refreg = WRef(key(kv),value(kv),RegKind(),FEMALE)
-;         val refwire = WRef(to-wire-name(key(kv)),value(kv),NodeKind(),MALE)
-;         val connect = Connect(refreg,refwire)
-;         inits = append(inits,list(connect))
-;      if empty?(inits) : s
-;      else :
-;         val pred = WRef(`reset, UIntType(IntWidth(1)), PortKind(), MALE)
-;         val when-reset = Conditionally(pred,Begin(inits),Begin(List<Stmt>()))
-;         Begin(list(s,when-reset))
-;
-;   defn rename (s:Stmt,h:HashTable<Symbol,True|False>) -> [Stmt HashTable<Symbol,Type>] :
-;      val t = HashTable<Symbol,Type>(symbol-hash)
-;      defn rename-expr (e:Expression) -> Expression :
-;         match(map(rename-expr,e)) :
-;            (e:WRegInit) : 
-;               val new-name = to-wire-name(name(reg(e) as WRef))
-;               WRef(new-name,type(reg(e)),RegKind(),gender(e))
-;            (e) : e
-;      defn rename-stmt (s:Stmt) -> Stmt :
-;         match(map(rename-stmt,s)) :
-;            (s:DefRegister) : 
-;               if h[name(s)] :
-;                  t[name(s)] = type(s)
-;                  Begin(list(s,DefWire(to-wire-name(name(s)),type(s))))
-;               else : s
-;            (s) : map(rename-expr,s)
-;      [rename-stmt(s) t]
-;
-;   defn init? (y:Symbol,s:Stmt) -> True|False :
-;      var used? = false
-;      defn has? (e:Expression) -> Expression :
-;         match(map(has?,e)) :
-;            (e:WRegInit) : 
-;               if name(reg(e) as WRef) == y : used? = true
-;            (e) : map(has?,e)
-;         e
-;      map(has?,s)
-;      used?
-;
-;   defn using-init (s:Stmt,h:HashTable<Symbol,True|False>) -> Stmt :
-;      match(s) :
-;         (s:DefRegister) : h[name(s)] = false
-;         (s) : 
-;            for x in h do :
-;               h[key(x)] = value(x) or init?(key(x),s)
-;      map(using-init{_,h},s)
-;
-;   defn explicit-init-scope (s:Stmt) -> Stmt :
-;      val h = HashTable<Symbol,True|False>(symbol-hash)
-;      using-init(s,h)
-;      ;println-debug(h)
-;      val [s* t] = rename(s,h)
-;      add-when(s*,t)
-;     
-;   Circuit(modules*, main(c)) where :
-;      val modules* = 
-;         for m in modules(c) map :
-;            Module(name(m), ports(m), body*) where :
-;               val body* = explicit-init-scope(body(m))
-
 ;;================ EXPAND WHENS =============================
 ; This pass does three things: remove last connect semantics,
 ;   remove conditional blocks, and eliminate concept of scoping.
@@ -1040,9 +965,6 @@ defn children (e:Expression) -> List<Expression> :
    map(f,e)
    to-list(es)
    
-
-
-
 ; ======= Symbolic Value Library ==========
 public definterface SymbolicValue
 public defstruct SVExp <: SymbolicValue :
@@ -1204,7 +1126,7 @@ defn expand-whens (s:Stmt, table:HashTable<Symbol,SymbolicValue>,decs:Vector<Stm
          add(decs,s)
          add{cons,_} $ Begin $ 
             for f in fields(type(module(s)) as BundleType) map :
-               if flip(f) == DEFAULT : 
+               if flip(f) == REVERSE : 
                   val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs
                   val x = to-symbol(split(to-string(n),'.')[0])
                   val f = to-symbol(split(to-string(n),'.')[1])
@@ -1270,7 +1192,7 @@ defn build-tables (s:Stmt,
          flattn[name(s)] = false
       (s:DefInstance) : ;TODO only add instance input ports. This probably involves correcting instance genders
          for f in fields(type(module(s)) as BundleType) do :
-            if flip(f) == DEFAULT : 
+            if flip(f) == REVERSE : 
                println-all-debug(["Instance: " s " has input " f])
                val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs
                assign[n] = SVNul()
diff --git a/test/chisel3/LFSR16.fir b/test/chisel3/LFSR16.fir
index a8857882..b635e4bf 100644
--- a/test/chisel3/LFSR16.fir
+++ b/test/chisel3/LFSR16.fir
@@ -3,12 +3,12 @@
 
 circuit LFSR16 : 
   module LFSR16 : 
-    output out : UInt(16)
-    input inc : UInt(1)
+    output out : UInt<16>
+    input inc : UInt<1>
     
-    node T_16 = UInt(1, 16)
-    reg res : UInt(16)
-    res.init := T_16
+    node T_16 = UInt<16>(1)
+    reg res : UInt<16>
+    on-reset res := T_16
     when inc : 
       node T_17 = bit(res, 0)
       node T_18 = bit(res, 2)
diff --git a/test/chisel3/MemorySearch.fir b/test/chisel3/MemorySearch.fir
index a2df4671..e62f35ba 100644
--- a/test/chisel3/MemorySearch.fir
+++ b/test/chisel3/MemorySearch.fir
@@ -2,43 +2,43 @@
 ; CHECK: Done!
 circuit MemorySearch : 
   module MemorySearch : 
-    input target : UInt(4)
-    output address : UInt(3)
-    input en : UInt(1)
-    output odone : UInt(1)
+    input target : UInt<4>
+    output address : UInt<3>
+    input en : UInt<1>
+    output odone : UInt<1>
     
-    node T_35 = UInt(0, 3)
-    reg index : UInt(3)
-    index.init := T_35
-    node T_36 = UInt(0, 1)
-    node T_37 = UInt(4, 3)
-    node T_38 = UInt(15, 4)
-    node T_39 = UInt(14, 4)
-    node T_40 = UInt(2, 2)
-    node T_41 = UInt(5, 3)
-    node T_42 = UInt(13, 4)
-    wire elts : UInt(1)[7]
-    elts.0 := T_36
-    elts.1 := T_37
-    elts.2 := T_38
-    elts.3 := T_39
-    elts.4 := T_40
-    elts.5 := T_41
-    elts.6 := T_42
+    node T_35 = UInt<3>(0)
+    reg index : UInt<3>
+    on-reset index := T_35
+    node T_36 = UInt<1>(0)
+    node T_37 = UInt<3>(4)
+    node T_38 = UInt<4>(15)
+    node T_39 = UInt<4>(14)
+    node T_40 = UInt<2>(2)
+    node T_41 = UInt<3>(5)
+    node T_42 = UInt<4>(13)
+    wire elts : UInt<1>[7]
+    elts[0] := T_36
+    elts[1] := T_37
+    elts[2] := T_38
+    elts[3] := T_39
+    elts[4] := T_40
+    elts[5] := T_41
+    elts[6] := T_42
     accessor elt = elts[index]
     node T_43 = bit-not(en)
     node T_44 = eq(elt, target)
-    node T_45 = UInt(7, 3)
+    node T_45 = UInt<3>(7)
     node T_46 = eq(index, T_45)
     node T_47 = bit-or(T_44, T_46)
     node done = bit-and(T_43, T_47)
     when en : 
-      node T_48 = UInt(0, 1)
+      node T_48 = UInt<1>(0)
       index := T_48
     else : 
       node T_49 = bit-not(done)
       when T_49 : 
-        node T_50 = UInt(1, 1)
+        node T_50 = UInt<1>(1)
         node T_51 = add(index, T_50)
         index := T_51
     odone := done
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index 7198667a..7379024b 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -2,29 +2,29 @@
 ; CHECK: Done!
 circuit ModuleVec : 
   module PlusOne : 
-    input in : UInt(32)
-    output out : UInt(32)
+    input in : UInt<32>
+    output out : UInt<32>
     
-    node T_33 = UInt(1, 1)
+    node T_33 = UInt<1>(1)
     node T_34 = add(in, T_33)
     out := T_34
   module PlusOne_25 : 
-    input in : UInt(32)
-    output out : UInt(32)
+    input in : UInt<32>
+    output out : UInt<32>
     
-    node T_35 = UInt(1, 1)
+    node T_35 = UInt<1>(1)
     node T_36 = add(in, T_35)
     out := T_36
   module ModuleVec : 
-    output ins : UInt(32)[2]
-    output outs : UInt(32)[2]
+    output ins : UInt<32>[2]
+    output outs : UInt<32>[2]
     
     inst T_37 of PlusOne
     inst T_38 of PlusOne_25
-    wire pluses : {flip in : UInt(32), out : UInt(32)}[2]
-    pluses.0 := T_37
-    pluses.1 := T_38
+    wire pluses : {flip in : UInt<32>, out : UInt<32>}[2]
+    pluses[0] := T_37
+    pluses[1] := T_38
     pluses.s.in := ins.s
-    outs.0 := pluses.s.out
-    pluses.s.in := ins.1
-    outs.1 := pluses.1.out
+    outs[0] := pluses.s.out
+    pluses.s.in := ins[1]
+    outs[1] := pluses[1].out
diff --git a/test/chisel3/Mul.fir b/test/chisel3/Mul.fir
index 4f954465..1ce6f797 100644
--- a/test/chisel3/Mul.fir
+++ b/test/chisel3/Mul.fir
@@ -2,43 +2,43 @@
 ; CHECK: Done!
 circuit Mul : 
   module Mul : 
-    input y : UInt(2)
-    input x : UInt(2)
-    output z : UInt(4)
+    input y : UInt<2>
+    input x : UInt<2>
+    output z : UInt<4>
     
-    node T_43 = UInt(0, 4)
-    node T_44 = UInt(0, 4)
-    node T_45 = UInt(0, 4)
-    node T_46 = UInt(0, 4)
-    node T_47 = UInt(0, 4)
-    node T_48 = UInt(1, 4)
-    node T_49 = UInt(2, 4)
-    node T_50 = UInt(3, 4)
-    node T_51 = UInt(0, 4)
-    node T_52 = UInt(2, 4)
-    node T_53 = UInt(4, 4)
-    node T_54 = UInt(6, 4)
-    node T_55 = UInt(0, 4)
-    node T_56 = UInt(3, 4)
-    node T_57 = UInt(6, 4)
-    node T_58 = UInt(9, 4)
-    wire tbl : UInt(4)[16]
-    tbl.0 := T_43
-    tbl.1 := T_44
-    tbl.2 := T_45
-    tbl.3 := T_46
-    tbl.4 := T_47
-    tbl.5 := T_48
-    tbl.6 := T_49
-    tbl.7 := T_50
-    tbl.8 := T_51
-    tbl.9 := T_52
-    tbl.10 := T_53
-    tbl.11 := T_54
-    tbl.12 := T_55
-    tbl.13 := T_56
-    tbl.14 := T_57
-    tbl.15 := T_58
+    node T_43 = UInt<4>(0)
+    node T_44 = UInt<4>(0)
+    node T_45 = UInt<4>(0)
+    node T_46 = UInt<4>(0)
+    node T_47 = UInt<4>(0)
+    node T_48 = UInt<4>(1)
+    node T_49 = UInt<4>(2)
+    node T_50 = UInt<4>(3)
+    node T_51 = UInt<4>(0)
+    node T_52 = UInt<4>(2)
+    node T_53 = UInt<4>(4)
+    node T_54 = UInt<4>(6)
+    node T_55 = UInt<4>(0)
+    node T_56 = UInt<4>(3)
+    node T_57 = UInt<4>(6)
+    node T_58 = UInt<4>(9)
+    wire tbl : UInt<4>[16]
+    tbl[0] := T_43
+    tbl[1] := T_44
+    tbl[2] := T_45
+    tbl[3] := T_46
+    tbl[4] := T_47
+    tbl[5] := T_48
+    tbl[6] := T_49
+    tbl[7] := T_50
+    tbl[8] := T_51
+    tbl[9] := T_52
+    tbl[10] := T_53
+    tbl[11] := T_54
+    tbl[12] := T_55
+    tbl[13] := T_56
+    tbl[14] := T_57
+    tbl[15] := T_58
     node T_60 = shl(x, 2)
     node T_61 = bit-or(T_60, y)
     accessor T_62 = tbl[T_61]
diff --git a/test/chisel3/Outer.fir b/test/chisel3/Outer.fir
index 227c5dae..2e1e4475 100644
--- a/test/chisel3/Outer.fir
+++ b/test/chisel3/Outer.fir
@@ -2,18 +2,18 @@
 ; CHECK: Done!
 circuit Outer : 
   module Inner : 
-    input in : UInt(8)
-    output out : UInt(8)
+    input in : UInt<8>
+    output out : UInt<8>
     
-    node T_14 = UInt(1, 1)
+    node T_14 = UInt<1>(1)
     node T_15 = add(in, T_14)
     out := T_15
   module Outer : 
-    input in : UInt(8)
-    output out : UInt(8)
+    input in : UInt<8>
+    output out : UInt<8>
     
     inst T_16 of Inner
     T_16.in := in
-    node T_17 = UInt(2, 2)
+    node T_17 = UInt<2>(2)
     node T_18 = mul(T_16.out, T_17)
     out := T_18
diff --git a/test/chisel3/RegisterVecShift.fir b/test/chisel3/RegisterVecShift.fir
index 7fae4c49..5a184366 100644
--- a/test/chisel3/RegisterVecShift.fir
+++ b/test/chisel3/RegisterVecShift.fir
@@ -2,35 +2,35 @@
 ; CHECK: Done!
 circuit RegisterVecShift : 
   module RegisterVecShift : 
-    input load : UInt(1)
-    output out : UInt(4)
-    input shift : UInt(1)
-    input ins : UInt(4)[4]
+    input load : UInt<1>
+    output out : UInt<4>
+    input shift : UInt<1>
+    input ins : UInt<4>[4]
     
-    reg delays : UInt(4)[4]
+    reg delays : UInt<4>[4]
     when reset : 
-      node T_39 = UInt(0, 4)
-      node T_40 = UInt(0, 4)
-      node T_41 = UInt(0, 4)
-      node T_42 = UInt(0, 4)
-      wire T_43 : UInt(4)[4]
-      T_43.0 := T_39
-      T_43.1 := T_40
-      T_43.2 := T_41
-      T_43.3 := T_42
+      node T_39 = UInt<4>(0)
+      node T_40 = UInt<4>(0)
+      node T_41 = UInt<4>(0)
+      node T_42 = UInt<4>(0)
+      wire T_43 : UInt<4>[4]
+      T_43[0] := T_39
+      T_43[1] := T_40
+      T_43[2] := T_41
+      T_43[3] := T_42
       delays := T_43
-    node T_44 = UInt(5, 3)
+    node T_44 = UInt<3>(5)
     node T_45 = bit-and(T_44, load)
-    node T_46 = UInt(4, 3)
+    node T_46 = UInt<3>(4)
     node T_47 = eq(T_45, T_46)
     when T_47 : 
-      delays.0 := ins.0
-      delays.1 := ins.1
-      delays.2 := ins.2
-      delays.3 := ins.3
+      delays[0] := ins[0]
+      delays[1] := ins[1]
+      delays[2] := ins[2]
+      delays[3] := ins[3]
      else : when shift : 
-        delays.0 := ins.0
-        delays.1 := delays.0
-        delays.2 := delays.1
-        delays.3 := delays.2
-    out := delays.3
+        delays[0] := ins[0]
+        delays[1] := delays[0]
+        delays[2] := delays[1]
+        delays[3] := delays[2]
+    out := delays[3]
diff --git a/test/chisel3/Stack.fir b/test/chisel3/Stack.fir
index fbd198eb..a6f33189 100644
--- a/test/chisel3/Stack.fir
+++ b/test/chisel3/Stack.fir
@@ -2,41 +2,41 @@
 ; CHECK: Done!
 circuit Stack : 
   module Stack : 
-    input push : UInt(1)
-    input pop : UInt(1)
-    input en : UInt(1)
-    output dataOut : UInt(32)
-    input dataIn : UInt(32)
+    input push : UInt<1>
+    input pop : UInt<1>
+    input en : UInt<1>
+    output dataOut : UInt<32>
+    input dataIn : UInt<32>
     
-    mem stack_mem : UInt(32)[16]
-    node T_30 = UInt(0, 5)
-    reg sp : UInt(5)
-    sp.init := T_30
-    node T_31 = UInt(0, 32)
-    reg out : UInt(32)
-    out.init := T_31
+    mem stack_mem : UInt<32>[16]
+    node T_30 = UInt<5>(0)
+    reg sp : UInt<5>
+    on-reset sp := T_30
+    node T_31 = UInt<32>(0)
+    reg out : UInt<32>
+    on-reset out := T_31
     when en : 
-      node T_32 = UInt(16, 5)
+      node T_32 = UInt<5>(16)
       node T_33 = lt(sp, T_32)
       node T_34 = bit-and(push, T_33)
       when T_34 : 
         accessor T_35 = stack_mem[sp]
         T_35 := dataIn
-        node T_36 = UInt(1, 1)
+        node T_36 = UInt<1>(1)
         node T_37 = add-wrap(sp, T_36)
         sp := T_37
       else : 
-        node T_38 = UInt(0, 1)
+        node T_38 = UInt<1>(0)
         node T_39 = gt(sp, T_38)
         node T_40 = bit-and(pop, T_39)
         when T_40 : 
-          node T_41 = UInt(1, 1)
+          node T_41 = UInt<1>(1)
           node T_42 = sub-wrap(sp, T_41)
           sp := T_42
-      node T_43 = UInt(0, 1)
+      node T_43 = UInt<1>(0)
       node T_44 = gt(sp, T_43)
       when T_44 : 
-        node T_45 = UInt(1, 1)
+        node T_45 = UInt<1>(1)
         node T_46 = sub-wrap(sp, T_45)
         accessor T_47 = stack_mem[T_46]
         out := T_47
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 0b6b19fa..6e3109a5 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -22,14 +22,14 @@ circuit top :
       when gt(x, y) :
       ;CHECK: when gt-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>
+         ;CHECK: inst s of subtracter@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>
          s.x := x
          s.y := y
          x := s.z
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.reset@<t:UInt> := reset@<t:UInt>
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
-         ;CHECK: s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
-         ;CHECK: x@<t:UInt> := s@<t:{ x : UInt@<t:UInt>, y : UInt@<t:UInt>, flip z : UInt@<t:UInt>, reset : UInt<1>@<t:UInt>}>.z@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.reset@<t:UInt> := reset@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.x@<t:UInt> := x@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.y@<t:UInt> := y@<t:UInt>
+         ;CHECK: x@<t:UInt> := s@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>,  z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}>.z@<t:UInt>      
       else :
          inst s2 of subtracter
          s2.x := x
diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir
index 3cd5c542..435540ae 100644
--- a/test/passes/infer-widths/gcd.fir
+++ b/test/passes/infer-widths/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefghijkl -p ctd | tee %s.out | FileCheck %s
 
 ;CHECK: Infer Widths
 circuit top :
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 2b73a8e9..f15980b3 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
 circuit top :
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index ca676ba5..722d569c 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s
 
 circuit top :
    module m :
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
new file mode 100644
index 00000000..4cd9f0cc
--- /dev/null
+++ b/test/passes/lower-to-ground/instance.fir
@@ -0,0 +1,35 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cdg | tee %s.out | FileCheck %s
+
+circuit top :
+   module source :
+      output data : UInt<16>
+      input ready : UInt<1>
+      data := UInt(16)
+   module sink :
+      input data : UInt<16>
+      output ready : UInt<1>
+   module top: 
+      wire connect : { data : UInt<16>, flip ready: UInt<1> }
+      wire connect2 : { flip data : UInt<16>, ready: UInt<1> }
+      inst src of source         
+      inst snk of sink           
+      connect := src   
+      connect2 := snk
+
+
+; CHECK: Resolve Genders
+
+; CHECK: connect@<g:f> := src@<g:m>
+; CHECK: connect2@<g:f> := snk@<g:m>
+
+; CHECK: Finished Resolve Genders
+
+
+; CHECK: Lower To Ground
+
+; CHECK: connect$data@<g:f> := src@<g:m>.data@<g:m>
+; CHECK: src@<g:m>.ready@<g:f> := connect$ready@<g:m>
+; CHECK: snk@<g:m>.data@<g:f> := connect2$data@<g:m>
+; CHECK: connect2$ready@<g:f> := snk@<g:m>.ready@<g:m>
+
+; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index 1e9c8f9f..95b125f6 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -5,6 +5,7 @@ circuit top :
    module q :
       wire i : UInt
       wire j : { x : UInt<32>, flip y : UInt<32> }
+      wire k : { x : UInt<32>, y : UInt<32> }
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
       ; CHECK: wire a$0$x : UInt<32>
@@ -19,16 +20,17 @@ circuit top :
       ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
 
-      mem m : { x : UInt<32>, flip y : UInt<32> }[2]
+      mem m : { x : UInt<32>, y : UInt<32> }[2]
       ; CHECK: mem m$x : UInt<32>[2]
       ; CHECK: mem m$y : UInt<32>[2]
 
       accessor c = m[i] ; MALE
       ; CHECK: accessor c$x = m$x[i]
       ; CHECK: accessor c$y = m$y[i]
-      ; CHECK: c$x := j$x
-      ; CHECK: j$y := c$y
-      c := j
+
+      c := k
+      ; CHECK: c$x := k$x
+      ; CHECK: c$y := k$y
 
 ; CHECK: Finished Lower To Ground
 
diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir
index 8cae8ba4..caf7d4b3 100644
--- a/test/passes/resolve-genders/accessor.fir
+++ b/test/passes/resolve-genders/accessor.fir
@@ -5,15 +5,15 @@ circuit top :
    module top :
       wire m : UInt<32>[10][10][10]
       wire i : UInt
-      accessor a = m[i] ;CHECK: accessor a = m@<g:male>[i@<g:male>]@<g:male>
-      accessor b = a[i] ;CHECK: accessor b = a@<g:male>[i@<g:male>]@<g:male>
-      accessor c = b[i] ;CHECK: accessor c = b@<g:male>[i@<g:male>]@<g:male>
+      accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m>
+      accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m>
+      accessor c = b[i] ;CHECK: accessor c = b@<g:m>[i@<g:m>]@<g:m>
       wire j : UInt
       j := c
 
-      accessor x = m[i] ;CHECK: accessor x = m@<g:female>[i@<g:male>]@<g:female>
-      accessor y = x[i] ;CHECK: accessor y = x@<g:female>[i@<g:male>]@<g:female>
-      accessor z = y[i] ;CHECK: accessor z = y@<g:female>[i@<g:male>]@<g:female>
+      accessor x = m[i] ;CHECK: accessor x = m@<g:f>[i@<g:m>]@<g:f>
+      accessor y = x[i] ;CHECK: accessor y = x@<g:f>[i@<g:m>]@<g:f>
+      accessor z = y[i] ;CHECK: accessor z = y@<g:f>[i@<g:m>]@<g:f>
       z := j
 
 ; CHECK: Finished Resolve Genders
diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir
index b16c9b66..2f7aae73 100644
--- a/test/passes/resolve-genders/gcd.fir
+++ b/test/passes/resolve-genders/gcd.fir
@@ -7,7 +7,7 @@ circuit top :
       input y : UInt
       output z : UInt
       z := sub-wrap(x, y)
-      ;CHECK: z@<g:female> := sub-wrap-uu(x@<g:male>, y@<g:male>)
+      ;CHECK: z@<g:f> := sub-wrap-uu(x@<g:m>, y@<g:m>)
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
@@ -20,15 +20,15 @@ circuit top :
       on-reset x := UInt(0)
       on-reset y := UInt(42)
       when gt(x, y) :
-      ;CHECK: when gt-uu(x@<g:male>, y@<g:male>) :
+      ;CHECK: when gt-uu(x@<g:m>, y@<g:m>) :
          inst s of subtracter
-         ;CHECK: inst s of subtracter@<g:female>
+         ;CHECK: inst s of subtracter@<g:m>
          s.x := x
          s.y := y
          x := s.z
-         ;CHECK: s@<g:female>.x@<g:female> := x@<g:male>
-         ;CHECK: s@<g:female>.y@<g:female> := y@<g:male>
-         ;CHECK: x@<g:female> := s@<g:female>.z@<g:male>
+         ;CHECK: s@<g:m>.x@<g:f> := x@<g:m>
+         ;CHECK: s@<g:m>.y@<g:f> := y@<g:m>
+         ;CHECK: x@<g:f> := s@<g:m>.z@<g:m>
       else :
          inst s2 of subtracter
          s2.x := x
diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir
index 3155dbcf..9bc67c21 100644
--- a/test/passes/resolve-genders/ports.fir
+++ b/test/passes/resolve-genders/ports.fir
@@ -11,11 +11,11 @@ circuit top :
       output ready : UInt<1>
    module top: 
       wire connect : { data : UInt<16>, flip ready: UInt<1> }
-      inst src of source         ;CHECK: inst src of source@<g:female>
-      inst snk of sink           ;CHECK: inst snk of sink@<g:female>
-      connect.data := src.data   ;CHECK: connect@<g:female>.data@<g:female> := src@<g:female>.data@<g:male>
-      src.ready := connect.ready ;CHECK: src@<g:female>.ready@<g:female> := connect@<g:female>.ready@<g:male>
-      snk.data := connect.data   ;CHECK: snk@<g:female>.data@<g:female> := connect@<g:male>.data@<g:male>
-      connect.ready := snk.ready ;CHECK: connect@<g:male>.ready@<g:female> := snk@<g:female>.ready@<g:male>
+      inst src of source         ;CHECK: inst src of source@<g:m>
+      inst snk of sink           ;CHECK: inst snk of sink@<g:m>
+      connect.data := src.data   ;CHECK: connect@<g:f>.data@<g:f> := src@<g:m>.data@<g:m>
+      src.ready := connect.ready ;CHECK: src@<g:m>.ready@<g:f> := connect@<g:f>.ready@<g:m>
+      snk.data := connect.data   ;CHECK: snk@<g:m>.data@<g:f> := connect@<g:m>.data@<g:m>
+      connect.ready := snk.ready ;CHECK: connect@<g:m>.ready@<g:f> := snk@<g:m>.ready@<g:m>
 
 ; CHECK: Finished Resolve Genders