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This approach uses the normal Unix mechanisms, rather than log grepping.
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This allows for testbench handling of pipelined reset,
independently of `PRINTF_COND.
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- Based upon stop value, use $fatal instead of $finish. This causes
the Verilog simulator to signal an error to the OS as appropriate.
- Don't guard stop with `PRINTF_COND (only not-`SYNTHESIS).
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trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
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Add simple documentation
trait PrimOp -> abstract class PrimOp
Move PrimOp case objects to object PrimOps
Rename PrimOp case objects to match concrete syntax
Overrwrite toString for more canonical serialization
Update some PrimOps utility functions
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trait Expression -> abstract class Expression
Ref -> Reference
abbrev. exp -> expr
Add abstract class Literal
UIntValue -> UIntLiteral extends Literal
SIntValue -> SIntLiteral extends Literal
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trait Stmt -> abstract class Statement (to match Expression)
abbrev. exp -> expr
BulkConnect -> PartialConnect
camelCase things that were snake_case
case class Empty() -> case object EmptyStmt
Change >120 character Statements to multiline
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Add simple documentation
trait Width -> abstract class Width
case class UnknownWidth -> case object UnknownWidth
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Add simple documentation
Flip -> Orientation
trait Orientation -> abstract class Orientation
Orientation case objects to upper camel case
REVERSE -> Flip
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trait Type -> abstract class Type
case class ClockType() -> case object ClockType
case class UnknownType() -> case object UnknownType
Add GroundType and AggregateType
ClockType has width of IntWidth(1)
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Add simple documentation
Change Direction case objects to upper camel case
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trait Module -> abstract class DefModule
InModule -> Module (match concrete syntax)
ExModule -> ExtModule (match concrete syntax)
Add simple scaladoc for each one
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In 7afe9f6180a53fd9f024c67d78289689a601c8b7, I reintroduced a performance
pathology when recursing through Mux trees. This patch prevents
redundantly expanding the same Mux more than a constant number of times,
preserving linear runtime but still resulting in acceptable QoR.
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Previously, we emitted if-else sequences for reg updates. Recent
improvements to FIRRTL resulted in the emission of explicit mux
networks instead. While equivalent, doing so reduces QoR, presumably
because ECAD tools are tuned to the habits of manual Verilog coders.
This seems to be a result of WRefs appearing between the regs and muxes.
Chasing down the sources of the WRefs corrects the code generation.
This patch reduces the Rocket pipeline area by about 2% and improves
rocket-chip's Verilator performance by about 8%.
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Fixes #187.
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Addresses #184
Problem was that the width inferencer must assume a minimal width
for self-referencing widths contained in a MaxWidth. Otherwise, it
cannot solve the constraint.
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Fix bug in FIRRTL width inference, refactor associated functions
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Update check high form
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Guard mem read ports with random data if read addr is out of range
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When folding over lists for MinWidth and MaxWidth, would assume 0 as a start
value. 0 persists through MinWidth resulting in under-constraining
The functions were also refactored to be more readable and aligned with scala
style/best practices.
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Add function for diff assignments for sim and synthesis to VerilogEmitter
Fixes #155
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Made obsolete by #120
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Canonicalizes catching/throwing PassExceptions.
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also check for it int unittest
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Fixes #147
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Transforms are new unit of modularity within the compiler.
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Add unit tests for splitting expressions and padding widths
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RemoveValidIf, SplitExpressions, and PadWidths
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This is to start moving stuff out of Emitter and into separate passes
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Changed initialization to assign the correct number of random bits.
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Fixes #133
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