Initializes register addresses. (#189)

Fixes #187.

1 files changed, 1 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index eb4cd9b8..14e8fbd7 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -416,6 +416,7 @@ class VerilogEmitter extends Emitter {
             val name = namespace.newTemp
             declare("reg",name,tpe(e))
             val exx = WRef(name,tpe(e),ExpKind(),UNKNOWNGENDER)
+            initialize(exx)
             update(exx,ex,clk,one)
             ex = exx
          }