From 0b4446fd9bb18f26150d6b21e129362b76ae2ac1 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Thu, 9 Jun 2016 17:27:25 -0700
Subject: Initializes register addresses. (#189)

Fixes #187.---
 src/main/scala/firrtl/Emitter.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index eb4cd9b8..14e8fbd7 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -416,6 +416,7 @@ class VerilogEmitter extends Emitter {
             val name = namespace.newTemp
             declare("reg",name,tpe(e))
             val exx = WRef(name,tpe(e),ExpKind(),UNKNOWNGENDER)
+            initialize(exx)
             update(exx,ex,clk,one)
             ex = exx
          }
-- 
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