Fix Verilog codegen for reg

Previously, we emitted if-else sequences for reg updates.  Recent
improvements to FIRRTL resulted in the emission of explicit mux
networks instead.  While equivalent, doing so reduces QoR, presumably
because ECAD tools are tuned to the habits of manual Verilog coders.

This seems to be a result of WRefs appearing between the regs and muxes.
Chasing down the sources of the WRefs corrects the code generation.

This patch reduces the Rocket pipeline area by about 2% and improves
rocket-chip's Verilator performance by about 8%.

1 files changed, 1 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 14e8fbd7..eb8eba32 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -320,7 +320,7 @@ class VerilogEmitter extends Emitter {
       }
       def update_and_reset(r: Expression, clk: Expression, reset: Expression, init: Expression) = {
         def addUpdate(e: Expression, tabs: String): Seq[Seq[Any]] = {
-          e match {
+          netlist.getOrElse(e, e) match {
             case m: Mux => {
               val ifStatement = Seq(tabs, "if(", m.cond, ") begin")
               val trueCase = addUpdate(m.tval, tabs + tab)