Emit correct Verilog for SIntLiteral

1 files changed, 9 insertions, 8 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 6b54e367..106e4355 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -129,14 +129,15 @@ class VerilogEmitter extends Emitter {
    //;------------- PASS -----------------
    def v_print (e:Expression) = {
       e match {
-         case (e:UIntLiteral) => {
-            val str = e.value.toString(16)
-            w.get.write(long_BANG(tpe(e)).toString + "'h" + str)
-         }
-         case (e:SIntLiteral) => {
-            val str = e.value.toString(16)
-            w.get.write(long_BANG(tpe(e)).toString + "'sh" + str)
-         }
+        case UIntLiteral(value, IntWidth(width)) => {
+          val str = s"$width'h${value.toString(16)}"
+          w.get.write(str)
+        }
+        case SIntLiteral(value, IntWidth(width)) => {
+          val unsignedValue = value + (if (value < 0) BigInt(1) << width.toInt else 0)
+          val str = s"$width'sh${unsignedValue.toString(16)}"
+          w.get.write(str)
+        }
       }
    }
    def op_stream (doprim:DoPrim) : Seq[Any] = {