API Cleanup - AST

trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._

37 files changed, 106 insertions, 71 deletions

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index 8efd010c..49bf9395 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -30,6 +30,7 @@ package firrtl
 import com.typesafe.scalalogging.LazyLogging
 import java.io.Writer
 
+import firrtl.ir._
 import Utils._
 import firrtl.passes._
 
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index b1a83b44..18074f7c 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -40,6 +40,7 @@ import firrtl.Serialize._
 import firrtl.Mappers._
 import firrtl.passes._
 import firrtl.PrimOps._
+import firrtl.ir._
 import WrappedExpression._
 // Datastructures
 import scala.collection.mutable.LinkedHashMap
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 3db83406..33cb70db 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -30,6 +30,7 @@ package firrtl
 import com.typesafe.scalalogging.LazyLogging
 import java.io.Writer
 import firrtl.passes.Pass
+import firrtl.ir.Circuit
 
 // ===========================================
 //              Utility Traits
@@ -67,7 +68,7 @@ class Chisel3ToHighFirrtl () extends Transform with SimpleRun {
       run(circuit, passSeq)
 }
 
-// Converts from the bare intermediate representation (IR.scala)
+// Converts from the bare intermediate representation (ir.scala)
 //  to a working representation (WIR.scala)
 class IRToWorkingIR () extends Transform with SimpleRun {
    val passSeq = Seq(passes.ToWorkingIR)
diff --git a/src/main/scala/firrtl/Mappers.scala b/src/main/scala/firrtl/Mappers.scala
index dc8c6d37..c00ca855 100644
--- a/src/main/scala/firrtl/Mappers.scala
+++ b/src/main/scala/firrtl/Mappers.scala
@@ -27,6 +27,8 @@ MODIFICATIONS.
 
 package firrtl
 
+import firrtl.ir._
+
 // TODO: Implement remaining mappers and recursive mappers
 object Mappers {
 
diff --git a/src/main/scala/firrtl/Namespace.scala b/src/main/scala/firrtl/Namespace.scala
index 1fc630d5..7d4758c5 100644
--- a/src/main/scala/firrtl/Namespace.scala
+++ b/src/main/scala/firrtl/Namespace.scala
@@ -28,6 +28,7 @@ MODIFICATIONS.
 package firrtl
 
 import scala.collection.mutable.HashSet
+import firrtl.ir._
 import Mappers._
 
 class Namespace private {
diff --git a/src/main/scala/firrtl/Parser.scala b/src/main/scala/firrtl/Parser.scala
index e6489b2f..dc8d6875 100644
--- a/src/main/scala/firrtl/Parser.scala
+++ b/src/main/scala/firrtl/Parser.scala
@@ -29,6 +29,7 @@ package firrtl
 import org.antlr.v4.runtime._;
 import org.antlr.v4.runtime.atn._;
 import com.typesafe.scalalogging.LazyLogging
+import firrtl.ir._
 import Utils.{time}
 import antlr._
 
@@ -40,7 +41,7 @@ case class InvalidEscapeCharException(message: String) extends ParserException(m
 
 object Parser extends LazyLogging
 {
-  /** Takes Iterator over lines of FIRRTL, returns AST (root node is Circuit) */
+  /** Takes Iterator over lines of FIRRTL, returns FirrtlNode (root node is Circuit) */
   def parse(lines: Iterator[String], infoMode: InfoMode = UseInfo): Circuit = {
     val fixedInput = time("Translator") { Translator.addBrackets(lines) }
     val antlrStream = new ANTLRInputStream(fixedInput.result)
diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala
index 5efa1b7d..c90260a3 100644
--- a/src/main/scala/firrtl/PrimOps.scala
+++ b/src/main/scala/firrtl/PrimOps.scala
@@ -27,9 +27,11 @@ MODIFICATIONS.
 
 package firrtl
 
+import firrtl.ir._
+
 import com.typesafe.scalalogging.LazyLogging
 
-/** Definitions and Utility functions for [[PrimOp]]s */
+/** Definitions and Utility functions for [[ir.PrimOp]]s */
 object PrimOps extends LazyLogging {
   /** Addition */
   case object Add extends PrimOp { override def toString = "add" }
@@ -101,9 +103,9 @@ object PrimOps extends LazyLogging {
         Dshl, Dshr, Neg, Cvt, Not, And, Or, Xor, Andr, Orr, Xorr, Cat, Bits, Head, Tail)
   private lazy val strToPrimOp: Map[String, PrimOp] = builtinPrimOps map (op => op.toString -> op) toMap
 
-  /** Seq of String representations of [[PrimOp]]s */
+  /** Seq of String representations of [[ir.PrimOp]]s */
   lazy val listing: Seq[String] = builtinPrimOps map (_.toString)
-  /** Gets the corresponding [[PrimOp]] from its String representation */
+  /** Gets the corresponding [[ir.PrimOp]] from its String representation */
   def fromString(op: String): PrimOp = strToPrimOp(op)
 
   // Borrowed from Stanza implementation
diff --git a/src/main/scala/firrtl/Serialize.scala b/src/main/scala/firrtl/Serialize.scala
index 9cb47efa..2c45c6ec 100644
--- a/src/main/scala/firrtl/Serialize.scala
+++ b/src/main/scala/firrtl/Serialize.scala
@@ -27,11 +27,12 @@ MODIFICATIONS.
 
 package firrtl
 
+import firrtl.ir._
 import firrtl.PrimOps._
 import firrtl.Utils._
 
 private object Serialize {
-  def serialize(root: AST): String = {
+  def serialize(root: FirrtlNode): String = {
     lazy val ser = new Serialize
     root match {
       case r: PrimOp => ser.serialize(r)
@@ -46,7 +47,7 @@ private object Serialize {
       case r: DefModule => ser.serialize(r)
       case r: Circuit => ser.serialize(r)
       case r: StringLit => ser.serialize(r)
-      case _ => throw new Exception("serialize called on unknown AST node!")
+      case _ => throw new Exception("serialize called on unknown FirrtlNode!")
     }
   }
   /** Creates new instance of Serialize */
diff --git a/src/main/scala/firrtl/StringLit.scala b/src/main/scala/firrtl/StringLit.scala
index b3d67064..501e9686 100644
--- a/src/main/scala/firrtl/StringLit.scala
+++ b/src/main/scala/firrtl/StringLit.scala
@@ -27,6 +27,8 @@ MODIFICATIONS.
 
 package firrtl
 
+import firrtl.ir._
+
 import java.nio.charset.StandardCharsets.UTF_8
 import scala.annotation.tailrec
 
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 830018c6..863f079f 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -43,10 +43,13 @@ import WrappedExpression._
 import firrtl.WrappedType._
 import firrtl.Mappers._
 import firrtl.PrimOps._
+import firrtl.ir._
 import scala.collection.mutable.ArrayBuffer
 import scala.collection.mutable.LinkedHashMap
 //import scala.reflect.runtime.universe._
 
+class FIRRTLException(str: String) extends Exception(str)
+
 object Utils extends LazyLogging {
   private[firrtl] def time[R](name: String)(block: => R): R = {
     logger.info(s"Starting $name")
@@ -277,9 +280,9 @@ object Utils extends LazyLogging {
 // =================================
    def error(str:String) = throw new FIRRTLException(str)
 
-   implicit class ASTUtils(ast: AST) {
+   implicit class FirrtlNodeUtils(node: FirrtlNode) {
      def getType(): Type = 
-       ast match {
+       node match {
          case e: Expression => e.getType
          case s: Statement => s.getType
          //case f: Field => f.getType
@@ -612,9 +615,9 @@ object Utils extends LazyLogging {
 
   /** Gets the root declaration of an expression
     *
-    * @param m    the [[firrtl.Module]] to search
-    * @param expr the [[firrtl.Expression]] that refers to some declaration
-    * @return the [[firrtl.IsDeclaration]] of `expr`
+    * @param m    the [[firrtl.ir.Module]] to search
+    * @param expr the [[firrtl.ir.Expression]] that refers to some declaration
+    * @return the [[firrtl.ir.IsDeclaration]] of `expr`
     * @throws DeclarationNotFoundException if no declaration of `expr` is found
     */
   def getDeclaration(m: Module, expr: Expression): IsDeclaration = {
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index db2e8b8b..91f9a0ce 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -42,14 +42,15 @@ import antlr._
 import PrimOps._
 import FIRRTLParser._
 import Parser.{InfoMode, IgnoreInfo, UseInfo, GenInfo, AppendInfo}
+import firrtl.ir._
 import scala.annotation.tailrec
 
-class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
+class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[FirrtlNode]
 {
   // Strip file path
   private def stripPath(filename: String) = filename.drop(filename.lastIndexOf("/")+1)
 
-  def visit[AST](ctx: FIRRTLParser.CircuitContext): Circuit = visitCircuit(ctx)
+  def visit[FirrtlNode](ctx: FIRRTLParser.CircuitContext): Circuit = visitCircuit(ctx)
 
   //  These regex have to change if grammar changes
   private def string2BigInt(s: String): BigInt = {
@@ -86,19 +87,21 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
     }
     infoMode match {
       case UseInfo =>
-        if (useInfo.length == 0) NoInfo else FileInfo(FIRRTLStringLitHandler.unescape(useInfo))
+        if (useInfo.length == 0) NoInfo
+        else ir.FileInfo(FIRRTLStringLitHandler.unescape(useInfo))
       case AppendInfo(filename) =>
         val newInfo = useInfo + ":" + genInfo(filename)
-        FileInfo(FIRRTLStringLitHandler.unescape(newInfo))
-      case GenInfo(filename) => FileInfo(FIRRTLStringLitHandler.unescape(genInfo(filename)))
+        ir.FileInfo(FIRRTLStringLitHandler.unescape(newInfo))
+      case GenInfo(filename) =>
+        ir.FileInfo(FIRRTLStringLitHandler.unescape(genInfo(filename)))
       case IgnoreInfo => NoInfo
     }
   }
 
-	private def visitCircuit[AST](ctx: FIRRTLParser.CircuitContext): Circuit =
+	private def visitCircuit[FirrtlNode](ctx: FIRRTLParser.CircuitContext): Circuit =
     Circuit(visitInfo(Option(ctx.info), ctx), ctx.module.map(visitModule), (ctx.id.getText))
     
-  private def visitModule[AST](ctx: FIRRTLParser.ModuleContext): DefModule = {
+  private def visitModule[FirrtlNode](ctx: FIRRTLParser.ModuleContext): DefModule = {
     val info = visitInfo(Option(ctx.info), ctx)
     ctx.getChild(0).getText match {
       case "module" => Module(info, ctx.id.getText, ctx.port.map(visitPort), visitBlock(ctx.block))
@@ -106,15 +109,15 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
     }
   }
 
-  private def visitPort[AST](ctx: FIRRTLParser.PortContext): Port = {
+  private def visitPort[FirrtlNode](ctx: FIRRTLParser.PortContext): Port = {
     Port(visitInfo(Option(ctx.info), ctx), (ctx.id.getText), visitDir(ctx.dir), visitType(ctx.`type`))
   }
-  private def visitDir[AST](ctx: FIRRTLParser.DirContext): Direction =
+  private def visitDir[FirrtlNode](ctx: FIRRTLParser.DirContext): Direction =
     ctx.getText match {
       case "input" => Input
       case "output" => Output
     }
-  private def visitMdir[AST](ctx: FIRRTLParser.MdirContext): MPortDir =
+  private def visitMdir[FirrtlNode](ctx: FIRRTLParser.MdirContext): MPortDir =
     ctx.getText match {
       case "infer" => MInfer
       case "read" => MRead
@@ -123,7 +126,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
     }
 
   // Match on a type instead of on strings?
-  private def visitType[AST](ctx: FIRRTLParser.TypeContext): Type = {
+  private def visitType[FirrtlNode](ctx: FIRRTLParser.TypeContext): Type = {
     ctx.getChild(0) match {
       case term: TerminalNode => 
         term.getText match {
@@ -138,18 +141,18 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
     }
   }
       
-	private def visitField[AST](ctx: FIRRTLParser.FieldContext): Field = {
+	private def visitField[FirrtlNode](ctx: FIRRTLParser.FieldContext): Field = {
     val flip = if(ctx.getChild(0).getText == "flip") Flip else Default
     Field((ctx.id.getText), flip, visitType(ctx.`type`))
   }
      
 
   // visitBlock
-	private def visitBlock[AST](ctx: FIRRTLParser.BlockContext): Statement =
+	private def visitBlock[FirrtlNode](ctx: FIRRTLParser.BlockContext): Statement =
     Begin(ctx.stmt.map(visitStmt)) 
 
   // Memories are fairly complicated to translate thus have a dedicated method
-  private def visitMem[AST](ctx: FIRRTLParser.StmtContext): Statement = {
+  private def visitMem[FirrtlNode](ctx: FIRRTLParser.StmtContext): Statement = {
     def parseChildren(children: Seq[ParseTree], map: Map[String, Seq[ParseTree]]): Map[String, Seq[ParseTree]] = {
       val field = children(0).getText
       if (field == "}") map
@@ -186,13 +189,13 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
   }
 
   // visitStringLit
-  private def visitStringLit[AST](node: TerminalNode): StringLit = {
+  private def visitStringLit[FirrtlNode](node: TerminalNode): StringLit = {
     val raw = node.getText.tail.init // Remove surrounding double quotes
     FIRRTLStringLitHandler.unescape(raw)
   }
 
   // visitStmt
-  private def visitStmt[AST](ctx: FIRRTLParser.StmtContext): Statement = {
+  private def visitStmt[FirrtlNode](ctx: FIRRTLParser.StmtContext): Statement = {
     val info = visitInfo(Option(ctx.info), ctx)
     ctx.getChild(0) match {
       case term: TerminalNode => term.getText match {
@@ -244,12 +247,12 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
      
   // add visitRuw ?
 	//T visitRuw(FIRRTLParser.RuwContext ctx);
-  //private def visitRuw[AST](ctx: FIRRTLParser.RuwContext): 
+  //private def visitRuw[FirrtlNode](ctx: FIRRTLParser.RuwContext): 
 
   // TODO 
   // - Add mux
   // - Add validif
-	private def visitExp[AST](ctx: FIRRTLParser.ExpContext): Expression = 
+	private def visitExp[FirrtlNode](ctx: FIRRTLParser.ExpContext): Expression = 
     if( ctx.getChildCount == 1 ) 
       Reference((ctx.getText), UnknownType)
     else
@@ -290,7 +293,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
   
   // stripSuffix("(") is included because in ANTLR concrete syntax we have to include open parentheses, 
   //  see grammar file for more details
-	private def visitPrimop[AST](ctx: FIRRTLParser.PrimopContext): PrimOp = fromString(ctx.getText.stripSuffix("("))
+	private def visitPrimop[FirrtlNode](ctx: FIRRTLParser.PrimopContext): PrimOp = fromString(ctx.getText.stripSuffix("("))
 
   // visit Id and Keyword?
 }
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index c2f880a3..f0c56358 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -30,6 +30,7 @@ package firrtl
 import scala.collection.Seq
 import Utils._
 import firrtl.Serialize._
+import firrtl.ir._
 import WrappedExpression._
 import WrappedWidth._
 
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/ir/IR.scala
index ab14bf43..f25ab144 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/ir/IR.scala
@@ -26,14 +26,8 @@ MODIFICATIONS.
 */
 
 package firrtl
+package ir
 
-import scala.collection.Seq
-
-// Should this be defined elsewhere?
-/*
-Structure containing source locator information.
-Member of most Stmt case classes.
-*/
 trait Info
 case object NoInfo extends Info {
   override def toString(): String = ""
@@ -42,9 +36,8 @@ case class FileInfo(info: StringLit) extends Info {
   override def toString(): String = " @[" + info.serialize + "]"
 }
 
-class FIRRTLException(str: String) extends Exception(str)
-
-trait AST {
+/** Intermediate Representation */
+abstract class FirrtlNode {
   def serialize: String = firrtl.Serialize.serialize(this)
 }
 
@@ -56,15 +49,15 @@ trait HasInfo {
 }
 trait IsDeclaration extends HasName with HasInfo
 
-case class StringLit(array: Array[Byte]) extends AST
+case class StringLit(array: Array[Byte]) extends FirrtlNode
 
 /** Primitive Operation
   *
   * See [[PrimOps]]
   */
-abstract class PrimOp extends AST
+abstract class PrimOp extends FirrtlNode
 
-abstract class Expression extends AST {
+abstract class Expression extends FirrtlNode {
   def tpe: Type
 }
 case class Reference(name: String, tpe: Type) extends Expression with HasName
@@ -85,7 +78,7 @@ case class SIntLiteral(value: BigInt, width: Width) extends Literal {
 }
 case class DoPrim(op: PrimOp, args: Seq[Expression], consts: Seq[BigInt], tpe: Type) extends Expression
 
-abstract class Statement extends AST
+abstract class Statement extends FirrtlNode
 case class DefWire(info: Info, name: String, tpe: Type) extends Statement with IsDeclaration
 case class DefRegister(
     info: Info,
@@ -124,7 +117,7 @@ case class Print(
     en: Expression) extends Statement with HasInfo
 case object EmptyStmt extends Statement
 
-abstract class Width extends AST {
+abstract class Width extends FirrtlNode {
   def +(x: Width): Width = (this, x) match {
     case (a: IntWidth, b: IntWidth) => IntWidth(a.width + b.width)
     case _ => UnknownWidth
@@ -147,14 +140,14 @@ case class IntWidth(width: BigInt) extends Width
 case object UnknownWidth extends Width
 
 /** Orientation of [[Field]] */
-abstract class Orientation extends AST
+abstract class Orientation extends FirrtlNode
 case object Default extends Orientation
 case object Flip extends Orientation
 
 /** Field of [[BundleType]] */
-case class Field(name: String, flip: Orientation, tpe: Type) extends AST with HasName
+case class Field(name: String, flip: Orientation, tpe: Type) extends FirrtlNode with HasName
 
-abstract class Type extends AST
+abstract class Type extends FirrtlNode
 abstract class GroundType extends Type {
   val width: Width
 }
@@ -169,15 +162,15 @@ case object ClockType extends GroundType {
 case object UnknownType extends Type
 
 /** [[Port]] Direction */
-abstract class Direction extends AST
+abstract class Direction extends FirrtlNode
 case object Input extends Direction
 case object Output extends Direction
 
 /** [[DefModule]] Port */
-case class Port(info: Info, name: String, direction: Direction, tpe: Type) extends AST with IsDeclaration
+case class Port(info: Info, name: String, direction: Direction, tpe: Type) extends FirrtlNode with IsDeclaration
 
 /** Base class for modules */
-abstract class DefModule extends AST with IsDeclaration {
+abstract class DefModule extends FirrtlNode with IsDeclaration {
   val info : Info
   val name : String
   val ports : Seq[Port]
@@ -193,5 +186,4 @@ case class Module(info: Info, name: String, ports: Seq[Port], body: Statement) e
   */
 case class ExtModule(info: Info, name: String, ports: Seq[Port]) extends DefModule
 
-case class Circuit(info: Info, modules: Seq[DefModule], main: String) extends AST with HasInfo
-
+case class Circuit(info: Info, modules: Seq[DefModule], main: String) extends FirrtlNode with HasInfo
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index d364f0dc..6d69b792 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -28,6 +28,7 @@ MODIFICATIONS.
 package firrtl.passes
 
 import firrtl._
+import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
 
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 5a4f613c..ebdd2469 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -34,6 +34,7 @@ import scala.collection.mutable.HashMap
 import scala.collection.mutable.ArrayBuffer
 
 import firrtl._
+import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
 import firrtl.Serialize._
diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
index f58572b1..7d4c96b2 100644
--- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
+++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
@@ -28,6 +28,7 @@ MODIFICATIONS.
 package firrtl.passes
 
 import firrtl._
+import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
 
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index f8fd5654..618a96c0 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -28,6 +28,7 @@ MODIFICATIONS.
 package firrtl.passes
 
 import firrtl._
+import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
 import firrtl.PrimOps._
diff --git a/src/main/scala/firrtl/passes/DeadCodeElimination.scala b/src/main/scala/firrtl/passes/DeadCodeElimination.scala
index 8482fe1d..80ba0e98 100644
--- a/src/main/scala/firrtl/passes/DeadCodeElimination.scala
+++ b/src/main/scala/firrtl/passes/DeadCodeElimination.scala
@@ -28,6 +28,7 @@ MODIFICATIONS.
 package firrtl.passes
 
 import firrtl._
+import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
 
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index e20ed793..b6e090f4 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -28,6 +28,7 @@ MODIFICATIONS.
 package firrtl.passes
 
 import firrtl._
+import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
 import firrtl.PrimOps._
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index d120426b..786de0eb 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -6,6 +6,7 @@ import scala.collection.mutable
 
 import firrtl.Mappers.{ExpMap,StmtMap}
 import firrtl.Utils.WithAs
+import firrtl.ir._
 
 
 // Tags an annotation to be consumed by this pass
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index d905fc34..b86b0651 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -30,16 +30,17 @@ package firrtl.passes
 import com.typesafe.scalalogging.LazyLogging
 
 import firrtl._
+import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
 
 // Datastructures
 import scala.collection.mutable.HashMap
 
-/** Removes all aggregate types from a [[Circuit]]
+/** Removes all aggregate types from a [[firrtl.ir.Circuit]]
   *
-  * @note Assumes [[firrtl.SubAccess]]es have been removed
-  * @note Assumes [[firrtl.Connect]]s and [[firrtl.IsInvalid]]s only operate on [[firrtl.Expression]]s of ground type
+  * @note Assumes [[firrtl.ir.SubAccess]]es have been removed
+  * @note Assumes [[firrtl.ir.Connect]]s and [[firrtl.ir.IsInvalid]]s only operate on [[firrtl.ir.Expression]]s of ground type
   * @example
   * {{{
   *   wire foo : { a : UInt<32>, b : UInt<16> }
@@ -54,8 +55,8 @@ object LowerTypes extends Pass {
 
   /** Delimiter used in lowering names */
   val delim = "_"
-  /** Expands a chain of referential [[firrtl.Expression]]s into the equivalent lowered name
-    * @param e [[firrtl.Expression]] made up of _only_ [[firrtl.WRef]], [[firrtl.WSubField]], and [[firrtl.WSubIndex]]
+  /** Expands a chain of referential [[firrtl.ir.Expression]]s into the equivalent lowered name
+    * @param e [[firrtl.ir.Expression]] made up of _only_ [[firrtl.WRef]], [[firrtl.WSubField]], and [[firrtl.WSubIndex]]
     * @return Lowered name of e
     */
   def loweredName(e: Expression): String = e match {
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 0d269a98..0cabc293 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -4,6 +4,7 @@ package passes
 import firrtl.Mappers.{ExpMap, StmtMap}
 import firrtl.Utils.{tpe, long_BANG}
 import firrtl.PrimOps._
+import firrtl.ir._
 
 // Makes all implicit width extensions and truncations explicit
 object PadWidths extends Pass {
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 739d0c2f..6b88c514 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -36,6 +36,7 @@ import scala.collection.mutable.HashMap
 import scala.collection.mutable.ArrayBuffer
 
 import firrtl._
+import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
 import firrtl.Serialize._
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
index 486e9ff8..a534cc50 100644
--- a/src/main/scala/firrtl/passes/RemoveValidIf.scala
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -1,6 +1,7 @@
 package firrtl
 package passes
 import firrtl.Mappers.{ExpMap, StmtMap}
+import firrtl.ir._
 
 // Removes ValidIf as an optimization
 object RemoveValidIf extends Pass {
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala
index 61f01e01..973e1be9 100644
--- a/src/main/scala/firrtl/passes/SplitExpressions.scala
+++ b/src/main/scala/firrtl/passes/SplitExpressions.scala
@@ -3,6 +3,7 @@ package passes
 
 import firrtl.Mappers.{ExpMap, StmtMap}
 import firrtl.Utils.{tpe, kind, gender, info}
+import firrtl.ir._
 import scala.collection.mutable
 
 
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index 3ad0c3dc..aa2c1d5d 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -31,12 +31,13 @@ import com.typesafe.scalalogging.LazyLogging
 import scala.annotation.tailrec
 
 import firrtl._
+import firrtl.ir._
 import firrtl.Utils._
 import firrtl.Mappers._
 
 /** Resolve name collisions that would occur in [[LowerTypes]]
   *
-  *  @note Must be run after [[InferTypes]] because [[DefNode]]s need type
+  *  @note Must be run after [[InferTypes]] because [[ir.DefNode]]s need type
   *  @example
   *  {{{
   *      wire a = { b, c }[2]
diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index 81a74b54..e04b4e14 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -6,8 +6,9 @@ import org.scalatest.FlatSpec
 import org.scalatest.Matchers
 import org.scalatest.junit.JUnitRunner
 
-import firrtl.{Parser,Circuit}
+import firrtl.ir.Circuit
 import firrtl.{
+   Parser,
    Named,
    ModuleName,
    ComponentName,
diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
index 49d5bc08..515bbfc8 100644
--- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala
+++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
@@ -30,7 +30,8 @@ package firrtlTests
 import java.io._
 import org.scalatest._
 import org.scalatest.prop._
-import firrtl._
+import firrtl.Parser
+import firrtl.ir.Circuit
 import firrtl.Parser.IgnoreInfo
 import firrtl.passes._
 
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 5c1b1a67..69645ddc 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -3,7 +3,8 @@ package firrtlTests
 import java.io._
 import org.scalatest._
 import org.scalatest.prop._
-import firrtl.{Parser,Circuit}
+import firrtl.Parser
+import firrtl.ir.Circuit
 import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassExceptions}
 
 class CheckSpec extends FlatSpec with Matchers {
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index 858d43b6..d3e02ff1 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -30,7 +30,8 @@ package firrtlTests
 import java.io._
 import org.scalatest._
 import org.scalatest.prop._
-import firrtl.{Parser,Circuit}
+import firrtl.Parser
+import firrtl.ir.Circuit
 import firrtl.passes._
 
 class ChirrtlSpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index f66b39e6..ce70a992 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -6,12 +6,13 @@ import org.scalatest.FlatSpec
 import org.scalatest.Matchers
 import org.scalatest.junit.JUnitRunner
 
-import firrtl.{Parser,Circuit}
+import firrtl.ir.Circuit
 import firrtl.{
    HighFirrtlCompiler,
    LowFirrtlCompiler,
    VerilogCompiler,
-   Compiler
+   Compiler,
+   Parser
 }
 
 /**
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index cfcb7f45..bfe58a2c 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -2,8 +2,9 @@ package firrtlTests
 
 import org.scalatest.Matchers
 import java.io.{StringWriter,Writer}
-import firrtl._
+import firrtl.ir.Circuit
 import firrtl.Parser.IgnoreInfo
+import firrtl.Parser
 import firrtl.passes._
 
 // Tests the following cases for constant propagation:
diff --git a/src/test/scala/firrtlTests/InlineInstancesTests.scala b/src/test/scala/firrtlTests/InlineInstancesTests.scala
index 52c01dc4..4a9f21bc 100644
--- a/src/test/scala/firrtlTests/InlineInstancesTests.scala
+++ b/src/test/scala/firrtlTests/InlineInstancesTests.scala
@@ -6,9 +6,10 @@ import org.scalatest.FlatSpec
 import org.scalatest.Matchers
 import org.scalatest.junit.JUnitRunner
 
-import firrtl.{Parser,Circuit}
+import firrtl.ir.Circuit
 import firrtl.passes.{PassExceptions,InlineCAKind}
 import firrtl.{
+   Parser,
    Named,
    ModuleName,
    ComponentName,
diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala
index 736849f5..e9096139 100644
--- a/src/test/scala/firrtlTests/LowerTypesSpec.scala
+++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala
@@ -4,7 +4,8 @@ package firrtlTests
 import java.io._
 import org.scalatest._
 import org.scalatest.prop._
-import firrtl.{Parser,Circuit}
+import firrtl.Parser
+import firrtl.ir.Circuit
 import firrtl.passes._
 
 class LowerTypesSpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/PassTests.scala b/src/test/scala/firrtlTests/PassTests.scala
index 38ecc7c3..efe7438c 100644
--- a/src/test/scala/firrtlTests/PassTests.scala
+++ b/src/test/scala/firrtlTests/PassTests.scala
@@ -4,7 +4,8 @@ import com.typesafe.scalalogging.LazyLogging
 import java.io.{StringWriter,Writer}
 import org.scalatest.{FlatSpec, Matchers}
 import org.scalatest.junit.JUnitRunner
-import firrtl.{Parser,Circuit,FIRRTLEmitter}
+import firrtl.{Parser,FIRRTLEmitter}
+import firrtl.ir.Circuit
 import firrtl.Parser.IgnoreInfo
 import firrtl.passes.{Pass, PassExceptions}
 import firrtl.{
diff --git a/src/test/scala/firrtlTests/UniquifySpec.scala b/src/test/scala/firrtlTests/UniquifySpec.scala
index 71f41074..6cc83c9c 100644
--- a/src/test/scala/firrtlTests/UniquifySpec.scala
+++ b/src/test/scala/firrtlTests/UniquifySpec.scala
@@ -30,7 +30,8 @@ package firrtlTests
 import java.io._
 import org.scalatest._
 import org.scalatest.prop._
-import firrtl.{Parser, Circuit}
+import firrtl.Parser
+import firrtl.ir.Circuit
 import firrtl.passes._
 
 class UniquifySpec extends FirrtlFlatSpec {
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 98693c61..ead55755 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -31,6 +31,7 @@ import java.io._
 import org.scalatest._
 import org.scalatest.prop._
 import firrtl._
+import firrtl.ir.Circuit
 import firrtl.passes._
 import firrtl.Parser.IgnoreInfo