API Cleanup - PrimOp & PrimOps

Add simple documentation
trait PrimOp -> abstract class PrimOp
Move PrimOp case objects to object PrimOps
Rename PrimOp case objects to match concrete syntax
Overrwrite toString for more canonical serialization
Update some PrimOps utility functions

10 files changed, 316 insertions, 316 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 1b171d3a..b1a83b44 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -39,6 +39,7 @@ import Utils._
 import firrtl.Serialize._
 import firrtl.Mappers._
 import firrtl.passes._
+import firrtl.PrimOps._
 import WrappedExpression._
 // Datastructures
 import scala.collection.mutable.LinkedHashMap
@@ -173,20 +174,20 @@ class VerilogEmitter extends Emitter {
       doprim.args foreach checkArgumentLegality
    
       doprim.op match {
-         case ADD_OP => Seq(cast_if(a0())," + ", cast_if(a1()))
-         case ADDW_OP => Seq(cast_if(a0())," + ", cast_if(a1()))
-         case SUB_OP => Seq(cast_if(a0())," - ", cast_if(a1()))
-         case SUBW_OP => Seq(cast_if(a0())," - ", cast_if(a1()))
-         case MUL_OP => Seq(cast_if(a0())," * ", cast_if(a1()) )
-         case DIV_OP => Seq(cast_if(a0())," / ", cast_if(a1()) )
-         case REM_OP => Seq(cast_if(a0())," % ", cast_if(a1()) )
-         case LESS_OP => Seq(cast_if(a0())," < ", cast_if(a1()))
-         case LESS_EQ_OP => Seq(cast_if(a0())," <= ", cast_if(a1()))
-         case GREATER_OP => Seq(cast_if(a0())," > ", cast_if(a1()))
-         case GREATER_EQ_OP => Seq(cast_if(a0())," >= ", cast_if(a1()))
-         case EQUAL_OP => Seq(cast_if(a0())," == ", cast_if(a1()))
-         case NEQUAL_OP => Seq(cast_if(a0())," != ", cast_if(a1()))
-         case PAD_OP => {
+         case Add => Seq(cast_if(a0())," + ", cast_if(a1()))
+         case Addw => Seq(cast_if(a0())," + ", cast_if(a1()))
+         case Sub => Seq(cast_if(a0())," - ", cast_if(a1()))
+         case Subw => Seq(cast_if(a0())," - ", cast_if(a1()))
+         case Mul => Seq(cast_if(a0())," * ", cast_if(a1()) )
+         case Div => Seq(cast_if(a0())," / ", cast_if(a1()) )
+         case Rem => Seq(cast_if(a0())," % ", cast_if(a1()) )
+         case Lt => Seq(cast_if(a0())," < ", cast_if(a1()))
+         case Leq => Seq(cast_if(a0())," <= ", cast_if(a1()))
+         case Gt => Seq(cast_if(a0())," > ", cast_if(a1()))
+         case Geq => Seq(cast_if(a0())," >= ", cast_if(a1()))
+         case Eq => Seq(cast_if(a0())," == ", cast_if(a1()))
+         case Neq => Seq(cast_if(a0())," != ", cast_if(a1()))
+         case Pad => {
             val w = long_BANG(tpe(a0()))
             val diff = (c0() - w)
             if (w == 0) Seq(a0())
@@ -200,70 +201,70 @@ class VerilogEmitter extends Emitter {
                case (t) => Seq("{{", diff, "'d0}, ", a0(), "}")
             }
          }
-         case AS_UINT_OP => Seq("$unsigned(",a0(),")")
-         case AS_SINT_OP => Seq("$signed(",a0(),")")
-         case AS_CLOCK_OP => Seq("$unsigned(",a0(),")")
-         case DSHLW_OP => Seq(cast(a0())," << ", a1())
-         case DYN_SHIFT_LEFT_OP => Seq(cast(a0())," << ", a1())
-         case DYN_SHIFT_RIGHT_OP => {
+         case AsUInt => Seq("$unsigned(",a0(),")")
+         case AsSInt => Seq("$signed(",a0(),")")
+         case AsClock => Seq("$unsigned(",a0(),")")
+         case Dshlw => Seq(cast(a0())," << ", a1())
+         case Dshl => Seq(cast(a0())," << ", a1())
+         case Dshr => {
             (doprim.tpe) match {
                case (t:SIntType) => Seq(cast(a0())," >>> ",a1())
                case (t) => Seq(cast(a0())," >> ",a1())
             }
          }
-         case SHLW_OP => Seq(cast(a0())," << ", c0())
-         case SHIFT_LEFT_OP => Seq(cast(a0())," << ",c0())
-         case SHIFT_RIGHT_OP => {
+         case Shlw => Seq(cast(a0())," << ", c0())
+         case Shl => Seq(cast(a0())," << ",c0())
+         case Shr => {
            if (c0 >= long_BANG(tpe(a0)))
              error("Verilog emitter does not support SHIFT_RIGHT >= arg width")
            Seq(a0(),"[", long_BANG(tpe(a0())) - 1,":",c0(),"]")
          }
-         case NEG_OP => Seq("-{",cast(a0()),"}")
-         case CONVERT_OP => {
+         case Neg => Seq("-{",cast(a0()),"}")
+         case Cvt => {
             tpe(a0()) match {
                case (t:UIntType) => Seq("{1'b0,",cast(a0()),"}")
                case (t:SIntType) => Seq(cast(a0()))
             }
          }
-         case NOT_OP => Seq("~ ",a0())
-         case AND_OP => Seq(cast_as(a0())," & ", cast_as(a1()))
-         case OR_OP => Seq(cast_as(a0())," | ", cast_as(a1()))
-         case XOR_OP => Seq(cast_as(a0())," ^ ", cast_as(a1()))
-         case AND_REDUCE_OP => {
+         case Not => Seq("~ ",a0())
+         case And => Seq(cast_as(a0())," & ", cast_as(a1()))
+         case Or => Seq(cast_as(a0())," | ", cast_as(a1()))
+         case Xor => Seq(cast_as(a0())," ^ ", cast_as(a1()))
+         case Andr => {
             val v = ArrayBuffer[Seq[Any]]()
             for (b <- 0 until long_BANG(doprim.tpe).toInt) {
                v += Seq(cast(a0()),"[",b,"]")
             }
             v.reduce(_ + " & " + _)
          }
-         case OR_REDUCE_OP => {
+         case Orr => {
             val v = ArrayBuffer[Seq[Any]]()
             for (b <- 0 until long_BANG(doprim.tpe).toInt) {
                v += Seq(cast(a0()),"[",b,"]")
             }
             v.reduce(_ + " | " + _)
          }
-         case XOR_REDUCE_OP => {
+         case Xorr => {
             val v = ArrayBuffer[Seq[Any]]()
             for (b <- 0 until long_BANG(doprim.tpe).toInt) {
                v += Seq(cast(a0()),"[",b,"]")
             }
             v.reduce(_ + " ^ " + _)
          }
-         case CONCAT_OP => Seq("{",cast(a0()),",",cast(a1()),"}")
-         case BITS_SELECT_OP => {
+         case Cat => Seq("{",cast(a0()),",",cast(a1()),"}")
+         case Bits => {
             // If selecting zeroth bit and single-bit wire, just emit the wire
             if (c0() == 0 && c1() == 0 && long_BANG(tpe(a0())) == 1) Seq(a0())
             else if (c0() == c1()) Seq(a0(),"[",c0(),"]")
             else Seq(a0(),"[",c0(),":",c1(),"]")
          }
-         case HEAD_OP => {
+         case Head => {
             val w = long_BANG(tpe(a0()))
             val high = w - 1
             val low = w - c0()
             Seq(a0(),"[",high,":",low,"]")
          }
-         case TAIL_OP => {
+         case Tail => {
             val w = long_BANG(tpe(a0()))
             val low = w - c0() - 1
             Seq(a0(),"[",low,":",0,"]")
@@ -504,7 +505,7 @@ class VerilogEmitter extends Emitter {
                   val enx = delay(en,s.readLatency,clk)
                   val mem_port = WSubAccess(mem,addrx,s.dataType,UNKNOWNGENDER)
                   val depthValue = UIntLiteral(s.depth, IntWidth(BigInt(s.depth).bitLength))
-                  val garbageGuard = DoPrim(GREATER_EQ_OP, Seq(addrx, depthValue), Seq(), UnknownType)
+                  val garbageGuard = DoPrim(Geq, Seq(addrx, depthValue), Seq(), UnknownType)
                   val garbageMux = Mux(garbageGuard, VRandom, mem_port, UnknownType)
                   synSimAssign(data, mem_port, garbageMux)
                }
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index 840fef03..ab14bf43 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -58,39 +58,11 @@ trait IsDeclaration extends HasName with HasInfo
 
 case class StringLit(array: Array[Byte]) extends AST
 
-trait PrimOp extends AST
-case object ADD_OP extends PrimOp 
-case object SUB_OP extends PrimOp
-case object MUL_OP extends PrimOp
-case object DIV_OP extends PrimOp
-case object REM_OP extends PrimOp
-case object LESS_OP extends PrimOp
-case object LESS_EQ_OP extends PrimOp
-case object GREATER_OP extends PrimOp
-case object GREATER_EQ_OP extends PrimOp
-case object EQUAL_OP extends PrimOp
-case object NEQUAL_OP extends PrimOp
-case object PAD_OP extends PrimOp
-case object AS_UINT_OP extends PrimOp
-case object AS_SINT_OP extends PrimOp
-case object AS_CLOCK_OP extends PrimOp
-case object SHIFT_LEFT_OP extends PrimOp
-case object SHIFT_RIGHT_OP extends PrimOp
-case object DYN_SHIFT_LEFT_OP extends PrimOp
-case object DYN_SHIFT_RIGHT_OP extends PrimOp
-case object CONVERT_OP extends PrimOp
-case object NEG_OP extends PrimOp
-case object NOT_OP extends PrimOp
-case object AND_OP extends PrimOp
-case object OR_OP extends PrimOp
-case object XOR_OP extends PrimOp
-case object AND_REDUCE_OP extends PrimOp
-case object OR_REDUCE_OP extends PrimOp
-case object XOR_REDUCE_OP extends PrimOp
-case object CONCAT_OP extends PrimOp
-case object BITS_SELECT_OP extends PrimOp
-case object HEAD_OP extends PrimOp
-case object TAIL_OP extends PrimOp
+/** Primitive Operation
+  *
+  * See [[PrimOps]]
+  */
+abstract class PrimOp extends AST
 
 abstract class Expression extends AST {
   def tpe: Type
diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala
index 5025f3a6..5efa1b7d 100644
--- a/src/main/scala/firrtl/PrimOps.scala
+++ b/src/main/scala/firrtl/PrimOps.scala
@@ -29,55 +29,82 @@ package firrtl
 
 import com.typesafe.scalalogging.LazyLogging
 
-import Utils._
-
+/** Definitions and Utility functions for [[PrimOp]]s */
 object PrimOps extends LazyLogging {
+  /** Addition */
+  case object Add extends PrimOp { override def toString = "add" }
+  /** Subtraction */
+  case object Sub extends PrimOp { override def toString = "sub" }
+  /** Multiplication */
+  case object Mul extends PrimOp { override def toString = "mul" }
+  /** Division */
+  case object Div extends PrimOp { override def toString = "div" }
+  /** Remainder */
+  case object Rem extends PrimOp { override def toString = "rem" }
+  /** Less Than */
+  case object Lt extends PrimOp { override def toString = "lt" }
+  /** Less Than Or Equal To */
+  case object Leq extends PrimOp { override def toString = "leq" }
+  /** Greater Than */
+  case object Gt extends PrimOp { override def toString = "gt" }
+  /** Greater Than Or Equal To */
+  case object Geq extends PrimOp { override def toString = "geq" }
+  /** Equal To */
+  case object Eq extends PrimOp { override def toString = "eq" }
+  /** Not Equal To */
+  case object Neq extends PrimOp { override def toString = "neq" }
+  /** Padding */
+  case object Pad extends PrimOp { override def toString = "pad" }
+  /** Interpret As UInt */
+  case object AsUInt extends PrimOp { override def toString = "asUInt" }
+  /** Interpret As SInt */
+  case object AsSInt extends PrimOp { override def toString = "asSInt" }
+  /** Interpret As Clock */
+  case object AsClock extends PrimOp { override def toString = "asClock" }
+  /** Static Shift Left */
+  case object Shl extends PrimOp { override def toString = "shl" }
+  /** Static Shift Right */
+  case object Shr extends PrimOp { override def toString = "shr" }
+  /** Dynamic Shift Left */
+  case object Dshl extends PrimOp { override def toString = "dshl" }
+  /** Dynamic Shift Right */
+  case object Dshr extends PrimOp { override def toString = "dshr" }
+  /** Arithmetic Convert to Signed */
+  case object Cvt extends PrimOp { override def toString = "cvt" }
+  /** Negate */
+  case object Neg extends PrimOp { override def toString = "neg" }
+  /** Bitwise Complement */
+  case object Not extends PrimOp { override def toString = "not" }
+  /** Bitwise And */
+  case object And extends PrimOp { override def toString = "and" }
+  /** Bitwise Or */
+  case object Or extends PrimOp { override def toString = "or" }
+  /** Bitwise Exclusive Or */
+  case object Xor extends PrimOp { override def toString = "xor" }
+  /** Bitwise And Reduce */
+  case object Andr extends PrimOp { override def toString = "andr" }
+  /** Bitwise Or Reduce */
+  case object Orr extends PrimOp { override def toString = "orr" }
+  /** Bitwise Exclusive Or Reduce */
+  case object Xorr extends PrimOp { override def toString = "xorr" }
+  /** Concatenate */
+  case object Cat extends PrimOp { override def toString = "cat" }
+  /** Bit Extraction */
+  case object Bits extends PrimOp { override def toString = "bits" }
+  /** Head */
+  case object Head extends PrimOp { override def toString = "head" }
+  /** Tail */
+  case object Tail extends PrimOp { override def toString = "tail" }
 
-  private val mapPrimOp2String = Map[PrimOp, String](
-    ADD_OP -> "add",
-    SUB_OP -> "sub",
-    MUL_OP -> "mul",
-    DIV_OP -> "div",
-    REM_OP -> "rem",
-    LESS_OP -> "lt",
-    LESS_EQ_OP -> "leq",
-    GREATER_OP -> "gt",
-    GREATER_EQ_OP -> "geq",
-    EQUAL_OP -> "eq",
-    NEQUAL_OP -> "neq",
-    PAD_OP -> "pad",
-    AS_UINT_OP -> "asUInt",
-    AS_SINT_OP -> "asSInt",
-    AS_CLOCK_OP -> "asClock",
-    SHIFT_LEFT_OP -> "shl",
-    SHIFT_RIGHT_OP -> "shr",
-    DYN_SHIFT_LEFT_OP -> "dshl",
-    DYN_SHIFT_RIGHT_OP -> "dshr",
-    NEG_OP -> "neg",
-    CONVERT_OP -> "cvt",
-    NOT_OP -> "not",
-    AND_OP -> "and",
-    OR_OP -> "or",
-    XOR_OP -> "xor",
-    AND_REDUCE_OP -> "andr",
-    OR_REDUCE_OP -> "orr",
-    XOR_REDUCE_OP -> "xorr",
-    CONCAT_OP -> "cat",
-    BITS_SELECT_OP -> "bits",
-    HEAD_OP -> "head",
-    TAIL_OP -> "tail",
-
-    //This are custom, we need to refactor to enable easily extending FIRRTL with custom primops
-    ADDW_OP -> "addw",
-    SUBW_OP -> "subw"
-  )
-  lazy val listing: Seq[String] = PrimOps.mapPrimOp2String.map { case (k,v) => v } toSeq
-  private val mapString2PrimOp = mapPrimOp2String.map(_.swap)
-  def fromString(op: String): PrimOp = mapString2PrimOp(op)
+  private lazy val builtinPrimOps: Seq[PrimOp] =
+    Seq(Add, Sub, Mul, Div, Rem, Lt, Leq, Gt, Geq, Eq, Neq, Pad, AsUInt, AsSInt, AsClock, Shl, Shr,
+        Dshl, Dshr, Neg, Cvt, Not, And, Or, Xor, Andr, Orr, Xorr, Cat, Bits, Head, Tail)
+  private lazy val strToPrimOp: Map[String, PrimOp] = builtinPrimOps map (op => op.toString -> op) toMap
 
-  implicit class PrimOpImplicits(op: PrimOp){
-    def getString(): String = mapPrimOp2String(op)
-  }
+  /** Seq of String representations of [[PrimOp]]s */
+  lazy val listing: Seq[String] = builtinPrimOps map (_.toString)
+  /** Gets the corresponding [[PrimOp]] from its String representation */
+  def fromString(op: String): PrimOp = strToPrimOp(op)
 
   // Borrowed from Stanza implementation
    def set_primop_type (e:DoPrim) : DoPrim = {
@@ -90,36 +117,36 @@ object PrimOps extends LazyLogging {
       val o = e.op
       val a = e.args
       val c = e.consts
-      def t1 () = tpe(a(0))
-      def t2 () = tpe(a(1))
-      def t3 () = tpe(a(2))
-      def w1 () = widthBANG(tpe(a(0)))
-      def w2 () = widthBANG(tpe(a(1)))
-      def w3 () = widthBANG(tpe(a(2)))
+      def t1 () = a(0).tpe
+      def t2 () = a(1).tpe
+      def t3 () = a(2).tpe
+      def w1 () = Utils.widthBANG(a(0).tpe)
+      def w2 () = Utils.widthBANG(a(1).tpe)
+      def w3 () = Utils.widthBANG(a(2).tpe)
       def c1 () = IntWidth(c(0))
       def c2 () = IntWidth(c(1))
       o match {
-         case ADD_OP => {
+         case Add => {
             val t = (t1(),t2()) match {
-               case (t1:UIntType, t2:UIntType) => UIntType(PLUS(MAX(w1(),w2()),ONE))
-               case (t1:UIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
-               case (t1:SIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
-               case (t1:SIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
+               case (t1:UIntType, t2:UIntType) => UIntType(PLUS(MAX(w1(),w2()),Utils.ONE))
+               case (t1:UIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE))
+               case (t1:SIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE))
+               case (t1:SIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE))
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case SUB_OP => {
+         case Sub => {
             val t = (t1(),t2()) match {
-               case (t1:UIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
-               case (t1:UIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
-               case (t1:SIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
-               case (t1:SIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
+               case (t1:UIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE))
+               case (t1:UIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE))
+               case (t1:SIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE))
+               case (t1:SIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),Utils.ONE))
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case MUL_OP => {
+         case Mul => {
             val t = (t1(),t2()) match {
                case (t1:UIntType, t2:UIntType) => UIntType(PLUS(w1(),w2()))
                case (t1:UIntType, t2:SIntType) => SIntType(PLUS(w1(),w2()))
@@ -129,87 +156,87 @@ object PrimOps extends LazyLogging {
             }
             DoPrim(o,a,c,t)
          }
-         case DIV_OP => {
+         case Div => {
             val t = (t1(),t2()) match {
                case (t1:UIntType, t2:UIntType) => UIntType(w1())
-               case (t1:UIntType, t2:SIntType) => SIntType(PLUS(w1(),ONE))
+               case (t1:UIntType, t2:SIntType) => SIntType(PLUS(w1(),Utils.ONE))
                case (t1:SIntType, t2:UIntType) => SIntType(w1())
-               case (t1:SIntType, t2:SIntType) => SIntType(PLUS(w1(),ONE))
+               case (t1:SIntType, t2:SIntType) => SIntType(PLUS(w1(),Utils.ONE))
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case REM_OP => {
+         case Rem => {
             val t = (t1(),t2()) match {
                case (t1:UIntType, t2:UIntType) => UIntType(MIN(w1(),w2()))
                case (t1:UIntType, t2:SIntType) => UIntType(MIN(w1(),w2()))
-               case (t1:SIntType, t2:UIntType) => SIntType(MIN(w1(),PLUS(w2(),ONE)))
+               case (t1:SIntType, t2:UIntType) => SIntType(MIN(w1(),PLUS(w2(),Utils.ONE)))
                case (t1:SIntType, t2:SIntType) => SIntType(MIN(w1(),w2()))
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case LESS_OP => {
+         case Lt => {
             val t = (t1(),t2()) match {
-               case (t1:UIntType, t2:UIntType) => BoolType()
-               case (t1:SIntType, t2:UIntType) => BoolType()
-               case (t1:UIntType, t2:SIntType) => BoolType()
-               case (t1:SIntType, t2:SIntType) => BoolType()
+               case (t1:UIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:UIntType, t2:SIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:SIntType) => Utils.BoolType()
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case LESS_EQ_OP => {
+         case Leq => {
             val t = (t1(),t2()) match {
-               case (t1:UIntType, t2:UIntType) => BoolType()
-               case (t1:SIntType, t2:UIntType) => BoolType()
-               case (t1:UIntType, t2:SIntType) => BoolType()
-               case (t1:SIntType, t2:SIntType) => BoolType()
+               case (t1:UIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:UIntType, t2:SIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:SIntType) => Utils.BoolType()
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case GREATER_OP => {
+         case Gt => {
             val t = (t1(),t2()) match {
-               case (t1:UIntType, t2:UIntType) => BoolType()
-               case (t1:SIntType, t2:UIntType) => BoolType()
-               case (t1:UIntType, t2:SIntType) => BoolType()
-               case (t1:SIntType, t2:SIntType) => BoolType()
+               case (t1:UIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:UIntType, t2:SIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:SIntType) => Utils.BoolType()
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case GREATER_EQ_OP => {
+         case Geq => {
             val t = (t1(),t2()) match {
-               case (t1:UIntType, t2:UIntType) => BoolType()
-               case (t1:SIntType, t2:UIntType) => BoolType()
-               case (t1:UIntType, t2:SIntType) => BoolType()
-               case (t1:SIntType, t2:SIntType) => BoolType()
+               case (t1:UIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:UIntType, t2:SIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:SIntType) => Utils.BoolType()
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case EQUAL_OP => {
+         case Eq => {
             val t = (t1(),t2()) match {
-               case (t1:UIntType, t2:UIntType) => BoolType()
-               case (t1:SIntType, t2:UIntType) => BoolType()
-               case (t1:UIntType, t2:SIntType) => BoolType()
-               case (t1:SIntType, t2:SIntType) => BoolType()
+               case (t1:UIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:UIntType, t2:SIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:SIntType) => Utils.BoolType()
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case NEQUAL_OP => {
+         case Neq => {
             val t = (t1(),t2()) match {
-               case (t1:UIntType, t2:UIntType) => BoolType()
-               case (t1:SIntType, t2:UIntType) => BoolType()
-               case (t1:UIntType, t2:SIntType) => BoolType()
-               case (t1:SIntType, t2:SIntType) => BoolType()
+               case (t1:UIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:UIntType) => Utils.BoolType()
+               case (t1:UIntType, t2:SIntType) => Utils.BoolType()
+               case (t1:SIntType, t2:SIntType) => Utils.BoolType()
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case PAD_OP => {
+         case Pad => {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(MAX(w1(),c1()))
                case (t1:SIntType) => SIntType(MAX(w1(),c1()))
@@ -217,25 +244,25 @@ object PrimOps extends LazyLogging {
             }
             DoPrim(o,a,c,t)
          }
-         case AS_UINT_OP => {
+         case AsUInt => {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(w1())
                case (t1:SIntType) => UIntType(w1())
-               case ClockType => UIntType(ONE)
+               case ClockType => UIntType(Utils.ONE)
                case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case AS_SINT_OP => {
+         case AsSInt => {
             val t = (t1()) match {
                case (t1:UIntType) => SIntType(w1())
                case (t1:SIntType) => SIntType(w1())
-               case ClockType => SIntType(ONE)
+               case ClockType => SIntType(Utils.ONE)
                case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case AS_CLOCK_OP => {
+         case AsClock => {
             val t = (t1()) match {
                case (t1:UIntType) => ClockType
                case (t1:SIntType) => ClockType
@@ -244,7 +271,7 @@ object PrimOps extends LazyLogging {
             }
             DoPrim(o,a,c,t)
          }
-         case SHIFT_LEFT_OP => {
+         case Shl => {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(PLUS(w1(),c1()))
                case (t1:SIntType) => SIntType(PLUS(w1(),c1()))
@@ -252,15 +279,15 @@ object PrimOps extends LazyLogging {
             }
             DoPrim(o,a,c,t)
          }
-         case SHIFT_RIGHT_OP => {
+         case Shr => {
             val t = (t1()) match {
-               case (t1:UIntType) => UIntType(MAX(MINUS(w1(),c1()),ONE))
-               case (t1:SIntType) => SIntType(MAX(MINUS(w1(),c1()),ONE))
+               case (t1:UIntType) => UIntType(MAX(MINUS(w1(),c1()),Utils.ONE))
+               case (t1:SIntType) => SIntType(MAX(MINUS(w1(),c1()),Utils.ONE))
                case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case DYN_SHIFT_LEFT_OP => {
+         case Dshl => {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(PLUS(w1(),POW(w2())))
                case (t1:SIntType) => SIntType(PLUS(w1(),POW(w2())))
@@ -268,7 +295,7 @@ object PrimOps extends LazyLogging {
             }
             DoPrim(o,a,c,t)
          }
-         case DYN_SHIFT_RIGHT_OP => {
+         case Dshr => {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(w1())
                case (t1:SIntType) => SIntType(w1())
@@ -276,23 +303,23 @@ object PrimOps extends LazyLogging {
             }
             DoPrim(o,a,c,t)
          }
-         case CONVERT_OP => {
+         case Cvt => {
             val t = (t1()) match {
-               case (t1:UIntType) => SIntType(PLUS(w1(),ONE))
+               case (t1:UIntType) => SIntType(PLUS(w1(),Utils.ONE))
                case (t1:SIntType) => SIntType(w1())
                case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case NEG_OP => {
+         case Neg => {
             val t = (t1()) match {
-               case (t1:UIntType) => SIntType(PLUS(w1(),ONE))
-               case (t1:SIntType) => SIntType(PLUS(w1(),ONE))
+               case (t1:UIntType) => SIntType(PLUS(w1(),Utils.ONE))
+               case (t1:SIntType) => SIntType(PLUS(w1(),Utils.ONE))
                case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case NOT_OP => {
+         case Not => {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(w1())
                case (t1:SIntType) => UIntType(w1())
@@ -300,70 +327,70 @@ object PrimOps extends LazyLogging {
             }
             DoPrim(o,a,c,t)
          }
-         case AND_OP => {
+         case And => {
             val t = (t1(),t2()) match {
                case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2()))
                case (t1,t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case OR_OP => {
+         case Or => {
             val t = (t1(),t2()) match {
                case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2()))
                case (t1,t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case XOR_OP => {
+         case Xor => {
             val t = (t1(),t2()) match {
                case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2()))
                case (t1,t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case AND_REDUCE_OP => {
+         case Andr => {
             val t = (t1()) match {
-               case (_:UIntType|_:SIntType) => BoolType()
+               case (_:UIntType|_:SIntType) => Utils.BoolType()
                case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case OR_REDUCE_OP => {
+         case Orr => {
             val t = (t1()) match {
-               case (_:UIntType|_:SIntType) => BoolType()
+               case (_:UIntType|_:SIntType) => Utils.BoolType()
                case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case XOR_REDUCE_OP => {
+         case Xorr => {
             val t = (t1()) match {
-               case (_:UIntType|_:SIntType) => BoolType()
+               case (_:UIntType|_:SIntType) => Utils.BoolType()
                case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case CONCAT_OP => {
+         case Cat => {
             val t = (t1(),t2()) match {
                case (_:UIntType|_:SIntType,_:UIntType|_:SIntType) => UIntType(PLUS(w1(),w2()))
                case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case BITS_SELECT_OP => {
+         case Bits => {
             val t = (t1()) match {
-               case (_:UIntType|_:SIntType) => UIntType(PLUS(MINUS(c1(),c2()),ONE))
+               case (_:UIntType|_:SIntType) => UIntType(PLUS(MINUS(c1(),c2()),Utils.ONE))
                case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case HEAD_OP => {
+         case Head => {
             val t = (t1()) match {
                case (_:UIntType|_:SIntType) => UIntType(c1())
                case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
-         case TAIL_OP => {
+         case Tail => {
             val t = (t1()) match {
                case (_:UIntType|_:SIntType) => UIntType(MINUS(w1(),c1()))
                case (t1) => UnknownType
diff --git a/src/main/scala/firrtl/Serialize.scala b/src/main/scala/firrtl/Serialize.scala
index e5bf166c..9cb47efa 100644
--- a/src/main/scala/firrtl/Serialize.scala
+++ b/src/main/scala/firrtl/Serialize.scala
@@ -60,7 +60,7 @@ class Serialize {
 
   def serialize(info: Info): String = " " + info.toString
 
-  def serialize(op: PrimOp): String = op.getString
+  def serialize(op: PrimOp): String = op.toString
 
   def serialize(lit: StringLit): String = FIRRTLStringLitHandler.escape(lit)
 
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 9f85949c..830018c6 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -42,6 +42,7 @@ import com.typesafe.scalalogging.LazyLogging
 import WrappedExpression._
 import firrtl.WrappedType._
 import firrtl.Mappers._
+import firrtl.PrimOps._
 import scala.collection.mutable.ArrayBuffer
 import scala.collection.mutable.LinkedHashMap
 //import scala.reflect.runtime.universe._
@@ -89,7 +90,7 @@ object Utils extends LazyLogging {
       else if ((e1 == we(zero)) | (e2 == we(zero))) zero
       else if (e1 == we(one)) e2.e1
       else if (e2 == we(one)) e1.e1
-      else DoPrim(AND_OP,Seq(e1.e1,e2.e1),Seq(),UIntType(IntWidth(1)))
+      else DoPrim(And,Seq(e1.e1,e2.e1),Seq(),UIntType(IntWidth(1)))
    }
    
    def OR (e1:WrappedExpression,e2:WrappedExpression) : Expression = {
@@ -97,13 +98,13 @@ object Utils extends LazyLogging {
       else if ((e1 == we(one)) | (e2 == we(one))) one
       else if (e1 == we(zero)) e2.e1
       else if (e2 == we(zero)) e1.e1
-      else DoPrim(OR_OP,Seq(e1.e1,e2.e1),Seq(),UIntType(IntWidth(1)))
+      else DoPrim(Or,Seq(e1.e1,e2.e1),Seq(),UIntType(IntWidth(1)))
    }
-   def EQV (e1:Expression,e2:Expression) : Expression = { DoPrim(EQUAL_OP,Seq(e1,e2),Seq(),tpe(e1)) }
+   def EQV (e1:Expression,e2:Expression) : Expression = { DoPrim(Eq,Seq(e1,e2),Seq(),tpe(e1)) }
    def NOT (e1:WrappedExpression) : Expression = {
       if (e1 == we(one)) zero
       else if (e1 == we(zero)) one
-      else DoPrim(EQUAL_OP,Seq(e1.e1,zero),Seq(),UIntType(IntWidth(1)))
+      else DoPrim(Eq,Seq(e1.e1,zero),Seq(),UIntType(IntWidth(1)))
    }
 
    
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index 3bff3e1e..c2f880a3 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -60,14 +60,13 @@ case object EmptyExpression extends Expression { def tpe = UnknownType }
 case class WDefInstance(info:Info,name:String,module:String,tpe:Type) extends Statement with IsDeclaration
 
 // Resultant width is the same as the maximum input width
-case object ADDW_OP extends PrimOp
+case object Addw extends PrimOp { override def toString = "addw" }
 // Resultant width is the same as the maximum input width
-case object SUBW_OP extends PrimOp
+case object Subw extends PrimOp { override def toString = "subw" }
 // Resultant width is the same as input argument width
-case object DSHLW_OP extends PrimOp
+case object Dshlw extends PrimOp { override def toString = "dshlw" }
 // Resultant width is the same as input argument width
-case object SHLW_OP extends PrimOp
-
+case object Shlw extends PrimOp { override def toString = "shlw" }
 
 object WrappedExpression {
    def apply (e:Expression) = new WrappedExpression(e)
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 1a11c0a4..5a4f613c 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -90,45 +90,45 @@ object CheckHighForm extends Pass with LazyLogging {
     def checkHighFormPrimop(e: DoPrim) = {
       def correctNum(ne: Option[Int], nc: Int) = {
         ne match {
-          case Some(i) => if(e.args.length != i) errors.append(new IncorrectNumArgsException(e.op.getString, i))
+          case Some(i) => if(e.args.length != i) errors.append(new IncorrectNumArgsException(e.op.toString, i))
           case None => // Do Nothing
         }
-        if (e.consts.length != nc) errors.append(new IncorrectNumConstsException(e.op.getString, nc))
+        if (e.consts.length != nc) errors.append(new IncorrectNumConstsException(e.op.toString, nc))
       }
 
       e.op match {
-        case ADD_OP             => correctNum(Option(2),0)
-        case SUB_OP             => correctNum(Option(2),0)
-        case MUL_OP             => correctNum(Option(2),0)
-        case DIV_OP             => correctNum(Option(2),0)
-        case REM_OP             => correctNum(Option(2),0)
-        case LESS_OP            => correctNum(Option(2),0)
-        case LESS_EQ_OP         => correctNum(Option(2),0)
-        case GREATER_OP         => correctNum(Option(2),0)
-        case GREATER_EQ_OP      => correctNum(Option(2),0)
-        case EQUAL_OP           => correctNum(Option(2),0)
-        case NEQUAL_OP          => correctNum(Option(2),0)
-        case PAD_OP             => correctNum(Option(1),1)
-        case AS_UINT_OP         => correctNum(Option(1),0)
-        case AS_SINT_OP         => correctNum(Option(1),0)
-        case AS_CLOCK_OP        => correctNum(Option(1),0)
-        case SHIFT_LEFT_OP      => correctNum(Option(1),1)
-        case SHIFT_RIGHT_OP     => correctNum(Option(1),1)
-        case DYN_SHIFT_LEFT_OP  => correctNum(Option(2),0)
-        case DYN_SHIFT_RIGHT_OP => correctNum(Option(2),0)
-        case CONVERT_OP         => correctNum(Option(1),0)
-        case NEG_OP             => correctNum(Option(1),0)
-        case NOT_OP             => correctNum(Option(1),0)
-        case AND_OP             => correctNum(Option(2),0)
-        case OR_OP              => correctNum(Option(2),0)
-        case XOR_OP             => correctNum(Option(2),0)
-        case AND_REDUCE_OP      => correctNum(None,0)
-        case OR_REDUCE_OP       => correctNum(None,0)
-        case XOR_REDUCE_OP      => correctNum(None,0)
-        case CONCAT_OP          => correctNum(Option(2),0)
-        case BITS_SELECT_OP     => correctNum(Option(1),2)
-        case HEAD_OP            => correctNum(Option(1),1)
-        case TAIL_OP            => correctNum(Option(1),1)
+        case Add => correctNum(Option(2),0)
+        case Sub => correctNum(Option(2),0)
+        case Mul => correctNum(Option(2),0)
+        case Div => correctNum(Option(2),0)
+        case Rem => correctNum(Option(2),0)
+        case Lt => correctNum(Option(2),0)
+        case Leq => correctNum(Option(2),0)
+        case Gt => correctNum(Option(2),0)
+        case Geq => correctNum(Option(2),0)
+        case Eq => correctNum(Option(2),0)
+        case Neq => correctNum(Option(2),0)
+        case Pad => correctNum(Option(1),1)
+        case AsUInt => correctNum(Option(1),0)
+        case AsSInt => correctNum(Option(1),0)
+        case AsClock => correctNum(Option(1),0)
+        case Shl => correctNum(Option(1),1)
+        case Shr => correctNum(Option(1),1)
+        case Dshl => correctNum(Option(2),0)
+        case Dshr => correctNum(Option(2),0)
+        case Cvt => correctNum(Option(1),0)
+        case Neg => correctNum(Option(1),0)
+        case Not => correctNum(Option(1),0)
+        case And => correctNum(Option(2),0)
+        case Or => correctNum(Option(2),0)
+        case Xor => correctNum(Option(2),0)
+        case Andr => correctNum(None,0)
+        case Orr => correctNum(None,0)
+        case Xorr => correctNum(None,0)
+        case Cat => correctNum(Option(2),0)
+        case Bits => correctNum(Option(1),2)
+        case Head => correctNum(Option(1),1)
+        case Tail => correctNum(Option(1),1)
       }
     }
 
@@ -318,38 +318,38 @@ object CheckTypes extends Pass with LazyLogging {
       }
       
       e.op match {
-         case AS_UINT_OP =>  {}
-         case AS_SINT_OP =>  {}
-         case AS_CLOCK_OP =>  {}
-         case DYN_SHIFT_LEFT_OP =>  is_uint(e.args(1)); all_ground(e.args)
-         case DYN_SHIFT_RIGHT_OP => is_uint(e.args(1)); all_ground(e.args)
-         case ADD_OP =>  all_ground(e.args)
-         case SUB_OP =>  all_ground(e.args)
-         case MUL_OP =>  all_ground(e.args)
-         case DIV_OP =>  all_ground(e.args)
-         case REM_OP =>  all_ground(e.args)
-         case LESS_OP =>  all_ground(e.args)
-         case LESS_EQ_OP =>  all_ground(e.args)
-         case GREATER_OP =>  all_ground(e.args)
-         case GREATER_EQ_OP =>  all_ground(e.args)
-         case EQUAL_OP =>  all_ground(e.args)
-         case NEQUAL_OP =>  all_ground(e.args)
-         case PAD_OP =>  all_ground(e.args)
-         case SHIFT_LEFT_OP =>  all_ground(e.args)
-         case SHIFT_RIGHT_OP =>  all_ground(e.args)
-         case CONVERT_OP =>  all_ground(e.args)
-         case NEG_OP =>  all_ground(e.args)
-         case NOT_OP =>  all_ground(e.args)
-         case AND_OP =>  all_ground(e.args)
-         case OR_OP =>  all_ground(e.args)
-         case XOR_OP =>  all_ground(e.args)
-         case AND_REDUCE_OP =>  all_ground(e.args)
-         case OR_REDUCE_OP =>  all_ground(e.args)
-         case XOR_REDUCE_OP =>  all_ground(e.args)
-         case CONCAT_OP =>  all_ground(e.args)
-         case BITS_SELECT_OP =>  all_ground(e.args)
-         case HEAD_OP =>  all_ground(e.args)
-         case TAIL_OP =>  all_ground(e.args)
+         case AsUInt =>
+         case AsSInt =>
+         case AsClock =>
+         case Dshl => is_uint(e.args(1)); all_ground(e.args)
+         case Dshr => is_uint(e.args(1)); all_ground(e.args)
+         case Add => all_ground(e.args)
+         case Sub => all_ground(e.args)
+         case Mul => all_ground(e.args)
+         case Div => all_ground(e.args)
+         case Rem => all_ground(e.args)
+         case Lt => all_ground(e.args)
+         case Leq => all_ground(e.args)
+         case Gt => all_ground(e.args)
+         case Geq => all_ground(e.args)
+         case Eq => all_ground(e.args)
+         case Neq => all_ground(e.args)
+         case Pad => all_ground(e.args)
+         case Shl => all_ground(e.args)
+         case Shr => all_ground(e.args)
+         case Cvt => all_ground(e.args)
+         case Neg => all_ground(e.args)
+         case Not => all_ground(e.args)
+         case And => all_ground(e.args)
+         case Or => all_ground(e.args)
+         case Xor => all_ground(e.args)
+         case Andr => all_ground(e.args)
+         case Orr => all_ground(e.args)
+         case Xorr => all_ground(e.args)
+         case Cat => all_ground(e.args)
+         case Bits => all_ground(e.args)
+         case Head => all_ground(e.args)
+         case Tail => all_ground(e.args)
       }
    }
       
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index e562f71d..f8fd5654 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -30,6 +30,7 @@ package firrtl.passes
 import firrtl._
 import firrtl.Utils._
 import firrtl.Mappers._
+import firrtl.PrimOps._
 
 import annotation.tailrec
 
@@ -137,10 +138,10 @@ object ConstProp extends Pass {
           case _ => false
         }
       x match {
-        case DoPrim(LESS_OP,      Seq(a,b),_,_) if(isUInt(a) && isZero(b)) => zero
-        case DoPrim(LESS_EQ_OP,   Seq(a,b),_,_) if(isZero(a) && isUInt(b)) => one
-        case DoPrim(GREATER_OP,   Seq(a,b),_,_) if(isZero(a) && isUInt(b)) => zero
-        case DoPrim(GREATER_EQ_OP,Seq(a,b),_,_) if(isUInt(a) && isZero(b)) => one
+        case DoPrim(Lt,  Seq(a,b),_,_) if(isUInt(a) && isZero(b)) => zero
+        case DoPrim(Leq, Seq(a,b),_,_) if(isZero(a) && isUInt(b)) => one
+        case DoPrim(Gt,  Seq(a,b),_,_) if(isZero(a) && isUInt(b)) => zero
+        case DoPrim(Geq, Seq(a,b),_,_) if(isUInt(a) && isZero(b)) => one
         case e => e
       }
     }
@@ -179,15 +180,15 @@ object ConstProp extends Pass {
           def r1 = range(e.args(1))
           e.op match {
             // Always true
-            case LESS_OP       if (r0 < r1) => one
-            case LESS_EQ_OP    if (r0 <= r1) => one
-            case GREATER_OP    if (r0 > r1) => one
-            case GREATER_EQ_OP if (r0 >= r1) => one
+            case Lt  if (r0 < r1) => one
+            case Leq if (r0 <= r1) => one
+            case Gt  if (r0 > r1) => one
+            case Geq if (r0 >= r1) => one
             // Always false
-            case LESS_OP       if (r0 >= r1) => zero
-            case LESS_EQ_OP    if (r0 > r1) => zero
-            case GREATER_OP    if (r0 <= r1) => zero
-            case GREATER_EQ_OP if (r0 < r1) => zero
+            case Lt  if (r0 >= r1) => zero
+            case Leq if (r0 > r1) => zero
+            case Gt  if (r0 <= r1) => zero
+            case Geq if (r0 < r1) => zero
             case _ => e
           }
         }
@@ -198,20 +199,20 @@ object ConstProp extends Pass {
   }
 
   private def constPropPrim(e: DoPrim): Expression = e.op match {
-    case SHIFT_LEFT_OP => foldShiftLeft(e)
-    case SHIFT_RIGHT_OP => foldShiftRight(e)
-    case CONCAT_OP => foldConcat(e)
-    case AND_OP => FoldAND(e)
-    case OR_OP => FoldOR(e)
-    case XOR_OP => FoldXOR(e)
-    case EQUAL_OP => FoldEqual(e)
-    case NEQUAL_OP => FoldNotEqual(e)
-    case LESS_OP|LESS_EQ_OP|GREATER_OP|GREATER_EQ_OP => foldComparison(e)
-    case NOT_OP => e.args(0) match {
+    case Shl => foldShiftLeft(e)
+    case Shr => foldShiftRight(e)
+    case Cat => foldConcat(e)
+    case And => FoldAND(e)
+    case Or => FoldOR(e)
+    case Xor => FoldXOR(e)
+    case Eq => FoldEqual(e)
+    case Neq => FoldNotEqual(e)
+    case (Lt | Leq | Gt | Geq) => foldComparison(e)
+    case Not => e.args(0) match {
       case UIntLiteral(v, IntWidth(w)) => UIntLiteral(v ^ ((BigInt(1) << w.toInt) - 1), IntWidth(w))
       case _ => e
     }
-    case BITS_SELECT_OP => e.args(0) match {
+    case Bits => e.args(0) match {
       case UIntLiteral(v, _) => {
         val hi = e.consts(0).toInt
         val lo = e.consts(1).toInt
@@ -220,7 +221,7 @@ object ConstProp extends Pass {
       }
       case x if long_BANG(tpe(e)) == long_BANG(tpe(x)) => tpe(x) match {
         case t: UIntType => x
-        case _ => DoPrim(AS_UINT_OP, Seq(x), Seq(), tpe(e))
+        case _ => DoPrim(AsUInt, Seq(x), Seq(), tpe(e))
       }
       case _ => e
     }
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 3054aab0..0d269a98 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -3,6 +3,7 @@ package passes
 
 import firrtl.Mappers.{ExpMap, StmtMap}
 import firrtl.Utils.{tpe, long_BANG}
+import firrtl.PrimOps._
 
 // Makes all implicit width extensions and truncations explicit
 object PadWidths extends Pass {
@@ -17,17 +18,15 @@ object PadWidths extends Pass {
          // default case should never be reached
       }
       if (i > width(e))
-         DoPrim(PAD_OP, Seq(e), Seq(i), tx)
+         DoPrim(Pad, Seq(e), Seq(i), tx)
       else if (i < width(e))
-         DoPrim(BITS_SELECT_OP, Seq(e), Seq(i - 1, 0), tx)
+         DoPrim(Bits, Seq(e), Seq(i - 1, 0), tx)
       else e
    }
    // Recursive, updates expression so children exp's have correct widths
    private def onExp(e: Expression): Expression = {
-      val sensitiveOps = Seq(
-         LESS_OP, LESS_EQ_OP, GREATER_OP, GREATER_EQ_OP, EQUAL_OP,
-         NEQUAL_OP, NOT_OP, AND_OP, OR_OP, XOR_OP, ADD_OP, SUB_OP,
-         MUL_OP, DIV_OP, REM_OP, SHIFT_RIGHT_OP)
+      val sensitiveOps = Seq( Lt, Leq, Gt, Geq, Eq, Neq, Not, And, Or, Xor,
+        Add, Sub, Mul, Div, Rem, Shr)
       val x = e map onExp
       x match {
          case Mux(cond, tval, fval, tpe) => {
@@ -40,15 +39,15 @@ object PadWidths extends Pass {
                val i = args.map(a => width(a)).foldLeft(0) {(a, b) => math.max(a, b)}
                x map fixup(i)
             }
-            case DYN_SHIFT_LEFT_OP => {
+            case Dshl => {
                // special case as args aren't all same width
                val ax = fixup(width(tpe))(args(0))
-               DoPrim(DSHLW_OP, Seq(ax, args(1)), consts, tpe)
+               DoPrim(Dshlw, Seq(ax, args(1)), consts, tpe)
             }
-            case SHIFT_LEFT_OP => {
+            case Shl => {
                // special case as arg should be same width as result
                val ax = fixup(width(tpe))(args(0))
-               DoPrim(SHLW_OP, Seq(ax), consts, tpe)
+               DoPrim(Shlw, Seq(ax), consts, tpe)
             }
             case _ => x
          }
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index ce1c7eed..739d0c2f 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -894,7 +894,7 @@ object RemoveAccesses extends Pass {
 object Legalize extends Pass {
   def name = "Legalize"
   def legalizeShiftRight (e: DoPrim): Expression = e.op match {
-    case SHIFT_RIGHT_OP => {
+    case Shr => {
       val amount = e.consts(0).toInt
       val width = long_BANG(tpe(e.args(0)))
       lazy val msb = width - 1
@@ -902,7 +902,7 @@ object Legalize extends Pass {
         e.tpe match {
           case t: UIntType => UIntLiteral(0, IntWidth(1))
           case t: SIntType =>
-            DoPrim(BITS_SELECT_OP, e.args, Seq(msb, msb), SIntType(IntWidth(1)))
+            DoPrim(Bits, e.args, Seq(msb, msb), SIntType(IntWidth(1)))
           case t => error(s"Unsupported type ${t} for Primop Shift Right")
         }
       } else {
@@ -920,7 +920,7 @@ object Legalize extends Pass {
         case _: UIntType => UIntType(IntWidth(w))
         case _: SIntType => SIntType(IntWidth(w))
       }
-      Connect(c.info, c.loc, DoPrim(BITS_SELECT_OP, Seq(c.expr), Seq(w-1, 0), newType))
+      Connect(c.info, c.loc, DoPrim(Bits, Seq(c.expr), Seq(w-1, 0), newType))
     }
   }
   def run (c: Circuit): Circuit = {
@@ -949,11 +949,11 @@ object VerilogWrap extends Pass {
       e map (v_wrap_e) match {
          case (e:DoPrim) => {
             def a0 () = e.args(0)
-            if (e.op == TAIL_OP) {
+            if (e.op == Tail) {
                (a0()) match {
                   case (e0:DoPrim) => {
-                     if (e0.op == ADD_OP) DoPrim(ADDW_OP,e0.args,Seq(),tpe(e))
-                     else if (e0.op == SUB_OP) DoPrim(SUBW_OP,e0.args,Seq(),tpe(e))
+                     if (e0.op == Add) DoPrim(Addw,e0.args,Seq(),tpe(e))
+                     else if (e0.op == Sub) DoPrim(Subw,e0.args,Seq(),tpe(e))
                      else e
                   }
                   case (e0) => e