API Cleanup - Statement

trait Stmt -> abstract class Statement (to match Expression)
abbrev. exp -> expr
BulkConnect -> PartialConnect
camelCase things that were snake_case
case class Empty() -> case object EmptyStmt
Change >120 character Statements to multiline

21 files changed, 263 insertions, 274 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 7af2017c..c8657131 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -275,15 +275,15 @@ class VerilogEmitter extends Emitter {
    def emit_verilog (m:Module) : DefModule = {
       mname = m.name
       val netlist = LinkedHashMap[WrappedExpression,Expression]()
-      val simlist = ArrayBuffer[Stmt]()
+      val simlist = ArrayBuffer[Statement]()
       val namespace = Namespace(m)
-      def build_netlist (s:Stmt) : Stmt = {
+      def build_netlist (s:Statement) : Statement = {
          s match {
-            case (s:Connect) => netlist(s.loc) = s.exp
+            case (s:Connect) => netlist(s.loc) = s.expr
             case (s:IsInvalid) => {
                val n = namespace.newTemp
-               val e = wref(n,tpe(s.exp))
-               netlist(s.exp) = e
+               val e = wref(n,tpe(s.expr))
+               netlist(s.expr) = e
             }
             case (s:Conditionally) => simlist += s
             case (s:DefNode) => {
@@ -379,10 +379,10 @@ class VerilogEmitter extends Emitter {
       }
       def initialize (e:Expression) = initials += Seq(e," = ",rand_string(tpe(e)),";")
       def initialize_mem(s: DefMemory) = {
-        val index = WRef("initvar", s.data_type, ExpKind(), UNKNOWNGENDER)
-        val rstring = rand_string(s.data_type)
+        val index = WRef("initvar", s.dataType, ExpKind(), UNKNOWNGENDER)
+        val rstring = rand_string(s.dataType)
         initials += Seq("for (initvar = 0; initvar < ", s.depth, "; initvar = initvar+1)")
-        initials += Seq(tab, WSubAccess(wref(s.name, s.data_type), index, s.data_type, FEMALE), " = ", rstring,";")
+        initials += Seq(tab, WSubAccess(wref(s.name, s.dataType), index, s.dataType, FEMALE), " = ", rstring,";")
       }
       def instantiate (n:String,m:String,es:Seq[Expression]) = {
          instdeclares += Seq(m," ",n," (")
@@ -447,9 +447,9 @@ class VerilogEmitter extends Emitter {
             }
          }}
       }
-      def build_streams (s:Stmt) : Stmt = {
+      def build_streams (s:Statement) : Statement = {
          s match {
-            case (s:Empty) => s
+            case EmptyStmt => s
             case (s:Connect) => s
             case (s:DefWire) => 
                declare("wire",s.name,s.tpe)
@@ -462,16 +462,10 @@ class VerilogEmitter extends Emitter {
                initialize(e)
             }
             case (s:IsInvalid) => {
-               val wref = netlist(s.exp).as[WRef].get
-               declare("reg",wref.name,tpe(s.exp))
+               val wref = netlist(s.expr).as[WRef].get
+               declare("reg",wref.name,tpe(s.expr))
                initialize(wref)
             }
-            case (s:DefPoison) => {
-               val n = s.name
-               val e = wref(n,s.tpe)
-               declare("reg",n,tpe(e))
-               initialize(e)
-            }
             case (s:DefNode) => {
                declare("wire",s.name,tpe(s.value))
                assign(WRef(s.name,tpe(s.value),NodeKind(),MALE),s.value)
@@ -491,7 +485,7 @@ class VerilogEmitter extends Emitter {
                   WSubField(x,f,t2,UNKNOWNGENDER)
                }
       
-               declare("reg",s.name,VectorType(s.data_type,s.depth))
+               declare("reg",s.name,VectorType(s.dataType,s.depth))
                initialize_mem(s)
                for (r <- s.readers ) {
                   val data = mem_exp(r,"data")
@@ -507,10 +501,10 @@ class VerilogEmitter extends Emitter {
                   //; Read port
                   assign(addr,netlist(addr)) //;Connects value to m.r.addr
                   assign(en,netlist(en))     //;Connects value to m.r.en
-                  val addrx = delay(addr,s.read_latency,clk)
-                  val enx = delay(en,s.read_latency,clk)
-                  val mem_port = WSubAccess(mem,addrx,s.data_type,UNKNOWNGENDER)
-                  val depthValue = UIntValue(s.depth, IntWidth(BigInt(s.depth).bitLength))
+                  val addrx = delay(addr,s.readLatency,clk)
+                  val enx = delay(en,s.readLatency,clk)
+                  val mem_port = WSubAccess(mem,addrx,s.dataType,UNKNOWNGENDER)
+                  val depthValue = UIntLiteral(s.depth, IntWidth(BigInt(s.depth).bitLength))
                   val garbageGuard = DoPrim(GREATER_EQ_OP, Seq(addrx, depthValue), Seq(), UnknownType)
                   val garbageMux = Mux(garbageGuard, VRandom, mem_port, UnknownType)
                   synSimAssign(data, mem_port, garbageMux)
@@ -535,11 +529,11 @@ class VerilogEmitter extends Emitter {
                   assign(mask,netlist(mask))
                   assign(en,netlist(en))
    
-                  val datax = delay(data,s.write_latency - 1,clk)
-                  val addrx = delay(addr,s.write_latency - 1,clk)
-                  val maskx = delay(mask,s.write_latency - 1,clk)
-                  val enx = delay(en,s.write_latency - 1,clk)
-                  val mem_port = WSubAccess(mem,addrx,s.data_type,UNKNOWNGENDER)
+                  val datax = delay(data,s.writeLatency - 1,clk)
+                  val addrx = delay(addr,s.writeLatency - 1,clk)
+                  val maskx = delay(mask,s.writeLatency - 1,clk)
+                  val enx = delay(en,s.writeLatency - 1,clk)
+                  val mem_port = WSubAccess(mem,addrx,s.dataType,UNKNOWNGENDER)
                   update(mem_port,datax,clk,AND(enx,maskx))
                }
    
@@ -569,18 +563,18 @@ class VerilogEmitter extends Emitter {
                   assign(wmode,netlist(wmode))
    
                   //; Delay new signals by latency
-                  val raddrx = delay(addr,s.read_latency,clk)
-                  val waddrx = delay(addr,s.write_latency - 1,clk)
-                  val enx = delay(en,s.write_latency - 1,clk)
-                  val rmodx = delay(wmode,s.write_latency - 1,clk)
-                  val datax = delay(data,s.write_latency - 1,clk)
-                  val maskx = delay(mask,s.write_latency - 1,clk)
+                  val raddrx = delay(addr,s.readLatency,clk)
+                  val waddrx = delay(addr,s.writeLatency - 1,clk)
+                  val enx = delay(en,s.writeLatency - 1,clk)
+                  val rmodx = delay(wmode,s.writeLatency - 1,clk)
+                  val datax = delay(data,s.writeLatency - 1,clk)
+                  val maskx = delay(mask,s.writeLatency - 1,clk)
    
                   //; Write 
    
-                  val rmem_port = WSubAccess(mem,raddrx,s.data_type,UNKNOWNGENDER)
+                  val rmem_port = WSubAccess(mem,raddrx,s.dataType,UNKNOWNGENDER)
                   assign(rdata,rmem_port)
-                  val wmem_port = WSubAccess(mem,waddrx,s.data_type,UNKNOWNGENDER)
+                  val wmem_port = WSubAccess(mem,waddrx,s.dataType,UNKNOWNGENDER)
 
                   val tempName = namespace.newTemp
                   val tempExp = AND(enx,maskx)
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index e11c2334..8bd8192b 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -109,22 +109,44 @@ case class SIntValue(value: BigInt, width: Width) extends Expression {
 }
 case class DoPrim(op: PrimOp, args: Seq[Expression], consts: Seq[BigInt], tpe: Type) extends Expression
 
-trait Stmt extends AST
-case class DefWire(info: Info, name: String, tpe: Type) extends Stmt with IsDeclaration
-case class DefPoison(info: Info, name: String, tpe: Type) extends Stmt with IsDeclaration
-case class DefRegister(info: Info, name: String, tpe: Type, clock: Expression, reset: Expression, init: Expression) extends Stmt with IsDeclaration
-case class DefInstance(info: Info, name: String, module: String) extends Stmt with IsDeclaration
-case class DefMemory(info: Info, name: String, data_type: Type, depth: Int, write_latency: Int, 
-               read_latency: Int, readers: Seq[String], writers: Seq[String], readwriters: Seq[String]) extends Stmt with IsDeclaration
-case class DefNode(info: Info, name: String, value: Expression) extends Stmt with IsDeclaration
-case class Conditionally(info: Info, pred: Expression, conseq: Stmt, alt: Stmt) extends Stmt with HasInfo
-case class Begin(stmts: Seq[Stmt]) extends Stmt
-case class BulkConnect(info: Info, loc: Expression, exp: Expression) extends Stmt with HasInfo
-case class Connect(info: Info, loc: Expression, exp: Expression) extends Stmt with HasInfo
-case class IsInvalid(info: Info, exp: Expression) extends Stmt with HasInfo
-case class Stop(info: Info, ret: Int, clk: Expression, en: Expression) extends Stmt with HasInfo
-case class Print(info: Info, string: StringLit, args: Seq[Expression], clk: Expression, en: Expression) extends Stmt with HasInfo
-case class Empty() extends Stmt
+abstract class Statement extends AST
+case class DefWire(info: Info, name: String, tpe: Type) extends Statement with IsDeclaration
+case class DefRegister(
+    info: Info,
+    name: String,
+    tpe: Type,
+    clock: Expression,
+    reset: Expression,
+    init: Expression) extends Statement with IsDeclaration
+case class DefInstance(info: Info, name: String, module: String) extends Statement with IsDeclaration
+case class DefMemory(
+    info: Info,
+    name: String,
+    dataType: Type,
+    depth: Int,
+    writeLatency: Int,
+    readLatency: Int,
+    readers: Seq[String],
+    writers: Seq[String],
+    readwriters: Seq[String]) extends Statement with IsDeclaration
+case class DefNode(info: Info, name: String, value: Expression) extends Statement with IsDeclaration
+case class Conditionally(
+    info: Info,
+    pred: Expression,
+    conseq: Statement,
+    alt: Statement) extends Statement with HasInfo
+case class Begin(stmts: Seq[Statement]) extends Statement
+case class PartialConnect(info: Info, loc: Expression, expr: Expression) extends Statement with HasInfo
+case class Connect(info: Info, loc: Expression, expr: Expression) extends Statement with HasInfo
+case class IsInvalid(info: Info, expr: Expression) extends Statement with HasInfo
+case class Stop(info: Info, ret: Int, clk: Expression, en: Expression) extends Statement with HasInfo
+case class Print(
+    info: Info,
+    string: StringLit,
+    args: Seq[Expression],
+    clk: Expression,
+    en: Expression) extends Statement with HasInfo
+case object EmptyStmt extends Statement
 
 abstract class Width extends AST {
   def +(x: Width): Width = (this, x) match {
@@ -188,7 +210,7 @@ abstract class DefModule extends AST with IsDeclaration {
   *
   * An instantiable hardware block
   */
-case class Module(info: Info, name: String, ports: Seq[Port], body: Stmt) extends DefModule
+case class Module(info: Info, name: String, ports: Seq[Port], body: Statement) extends DefModule
 /** External Module
   *
   * Generally used for Verilog black boxes
diff --git a/src/main/scala/firrtl/Mappers.scala b/src/main/scala/firrtl/Mappers.scala
index 0ee8165b..aeb67f3d 100644
--- a/src/main/scala/firrtl/Mappers.scala
+++ b/src/main/scala/firrtl/Mappers.scala
@@ -32,41 +32,40 @@ object Mappers {
 
   // ********** Stmt Mappers **********
   private trait StmtMagnet {
-    def map(stmt: Stmt): Stmt
+    def map(stmt: Statement): Statement
   }
   private object StmtMagnet {
-    implicit def forStmt(f: Stmt => Stmt) = new StmtMagnet {
-      override def map(stmt: Stmt): Stmt = {
+    implicit def forStmt(f: Statement => Statement) = new StmtMagnet {
+      override def map(stmt: Statement): Statement = {
         stmt match {
           case s: Conditionally => Conditionally(s.info, s.pred, f(s.conseq), f(s.alt))
           case s: Begin => Begin(s.stmts.map(f))
-          case s: Stmt => s
+          case s: Statement => s
         }
       }
     }
     implicit def forExp(f: Expression => Expression) = new StmtMagnet {
-      override def map(stmt: Stmt): Stmt = {
+      override def map(stmt: Statement): Statement = {
         stmt match { 
           case s: DefRegister => DefRegister(s.info, s.name, s.tpe, f(s.clock), f(s.reset), f(s.init))
           case s: DefNode => DefNode(s.info, s.name, f(s.value))
-          case s: Connect => Connect(s.info, f(s.loc), f(s.exp))
-          case s: BulkConnect => BulkConnect(s.info, f(s.loc), f(s.exp))
+          case s: Connect => Connect(s.info, f(s.loc), f(s.expr))
+          case s: PartialConnect => PartialConnect(s.info, f(s.loc), f(s.expr))
           case s: Conditionally => Conditionally(s.info, f(s.pred), s.conseq, s.alt)
-          case s: IsInvalid => IsInvalid(s.info, f(s.exp))
+          case s: IsInvalid => IsInvalid(s.info, f(s.expr))
           case s: Stop => Stop(s.info, s.ret, f(s.clk), f(s.en))
           case s: Print => Print(s.info, s.string, s.args.map(f), f(s.clk), f(s.en))
           case s: CDefMPort => CDefMPort(s.info,s.name,s.tpe,s.mem,s.exps.map(f),s.direction)
-          case s: Stmt => s 
+          case s: Statement => s
         }
       }
     }
     implicit def forType(f: Type => Type) = new StmtMagnet {
-      override def map(stmt: Stmt) : Stmt = {
+      override def map(stmt: Statement) : Statement = {
         stmt match {
-          case s:DefPoison => DefPoison(s.info,s.name,f(s.tpe))
           case s:DefWire => DefWire(s.info,s.name,f(s.tpe))
           case s:DefRegister => DefRegister(s.info,s.name,f(s.tpe),s.clock,s.reset,s.init)
-          case s:DefMemory => DefMemory(s.info,s.name, f(s.data_type), s.depth, s.write_latency, s.read_latency, s.readers, s.writers, s.readwriters)
+          case s:DefMemory => DefMemory(s.info,s.name, f(s.dataType), s.depth, s.writeLatency, s.readLatency, s.readers, s.writers, s.readwriters)
           case s:CDefMemory => CDefMemory(s.info,s.name, f(s.tpe), s.size, s.seq)
           case s:CDefMPort => CDefMPort(s.info,s.name, f(s.tpe), s.mem, s.exps,s.direction)
           case s => s
@@ -74,12 +73,11 @@ object Mappers {
       }
     }
     implicit def forString(f: String => String) = new StmtMagnet {
-      override def map(stmt: Stmt): Stmt = {
+      override def map(stmt: Statement): Statement = {
         stmt match {
           case s: DefWire => DefWire(s.info,f(s.name),s.tpe)
-          case s: DefPoison => DefPoison(s.info,f(s.name),s.tpe)
           case s: DefRegister => DefRegister(s.info,f(s.name), s.tpe, s.clock, s.reset, s.init)
-          case s: DefMemory => DefMemory(s.info,f(s.name), s.data_type, s.depth, s.write_latency, s.read_latency, s.readers, s.writers, s.readwriters)
+          case s: DefMemory => DefMemory(s.info,f(s.name), s.dataType, s.depth, s.writeLatency, s.readLatency, s.readers, s.writers, s.readwriters)
           case s: DefNode => DefNode(s.info,f(s.name),s.value)
           case s: DefInstance => DefInstance(s.info,f(s.name), s.module)
           case s: WDefInstance => WDefInstance(s.info,f(s.name), s.module,s.tpe)
@@ -90,9 +88,9 @@ object Mappers {
       }
     }
   }
-  implicit class StmtMap(stmt: Stmt) {
+  implicit class StmtMap(stmt: Statement) {
     // Using implicit types to allow overloading of function type to map, see StmtMagnet above
-    def map[T](f: T => T)(implicit magnet: (T => T) => StmtMagnet): Stmt = magnet(f).map(stmt)
+    def map[T](f: T => T)(implicit magnet: (T => T) => StmtMagnet): Statement = magnet(f).map(stmt)
   }
 
   // ********** Expression Mappers **********
@@ -199,7 +197,7 @@ object Mappers {
     def map(module: DefModule): DefModule
   }
   private object ModuleMagnet {
-    implicit def forStmt(f: Stmt => Stmt) = new ModuleMagnet {
+    implicit def forStmt(f: Statement => Statement) = new ModuleMagnet {
       override def map(module: DefModule): DefModule = {
         module match {
           case m: Module => Module(m.info, m.name, m.ports, f(m.body))
diff --git a/src/main/scala/firrtl/Namespace.scala b/src/main/scala/firrtl/Namespace.scala
index 8e89cbf2..1fc630d5 100644
--- a/src/main/scala/firrtl/Namespace.scala
+++ b/src/main/scala/firrtl/Namespace.scala
@@ -62,7 +62,7 @@ object Namespace {
   def apply(m: DefModule): Namespace = {
     val namespace = new Namespace
 
-    def buildNamespaceStmt(s: Stmt): Stmt =
+    def buildNamespaceStmt(s: Statement): Statement =
       s map buildNamespaceStmt match {
         case dec: IsDeclaration =>
           namespace.namespace += dec.name
diff --git a/src/main/scala/firrtl/Serialize.scala b/src/main/scala/firrtl/Serialize.scala
index e81ecba9..cec1271f 100644
--- a/src/main/scala/firrtl/Serialize.scala
+++ b/src/main/scala/firrtl/Serialize.scala
@@ -36,7 +36,7 @@ private object Serialize {
     root match {
       case r: PrimOp => ser.serialize(r)
       case r: Expression => ser.serialize(r)
-      case r: Stmt => ser.serialize(r)
+      case r: Statement => ser.serialize(r)
       case r: Width => ser.serialize(r)
       case r: Orientation => ser.serialize(r)
       case r: Field => ser.serialize(r)
@@ -84,7 +84,7 @@ class Serialize {
     }
   }
 
-  def serialize(stmt: Stmt): String = {
+  def serialize(stmt: Statement): String = {
     stmt match {
       case w: DefWire => s"wire ${w.name} : ${serialize(w.tpe)}${w.info}"
       case r: DefRegister =>
@@ -99,10 +99,10 @@ class Serialize {
         val str = new StringBuilder(s"mem ${m.name} :${m.info}")
         withIndent {
           str ++= newline +
-            s"data-type => ${serialize(m.data_type)}" + newline +
+            s"data-type => ${serialize(m.dataType)}" + newline +
             s"depth => ${m.depth}" + newline +
-            s"read-latency => ${m.read_latency}" + newline +
-            s"write-latency => ${m.write_latency}" + newline +
+            s"read-latency => ${m.readLatency}" + newline +
+            s"write-latency => ${m.writeLatency}" + newline +
             (if (m.readers.nonEmpty) m.readers.map(r => s"reader => ${r}").mkString(newline) + newline
              else "") +
             (if (m.writers.nonEmpty) m.writers.map(w => s"writer => ${w}").mkString(newline) + newline
@@ -114,13 +114,13 @@ class Serialize {
         str.result
       }
       case n: DefNode => s"node ${n.name} = ${serialize(n.value)}${n.info}"
-      case c: Connect => s"${serialize(c.loc)} <= ${serialize(c.exp)}${c.info}"
-      case b: BulkConnect => s"${serialize(b.loc)} <- ${serialize(b.exp)}${b.info}"
+      case c: Connect => s"${serialize(c.loc)} <= ${serialize(c.expr)}${c.info}"
+      case p: PartialConnect => s"${serialize(p.loc)} <- ${serialize(p.expr)}${p.info}"
       case w: Conditionally => {
         var str = new StringBuilder(s"when ${serialize(w.pred)} :${w.info}")
         withIndent { str ++= newline + serialize(w.conseq) }
         w.alt match {
-          case s:Empty => str.result
+          case EmptyStmt => str.result
           case s => {
             str ++= newline + "else :"
             withIndent { str ++= newline + serialize(w.alt) }
@@ -136,7 +136,7 @@ class Serialize {
         }
         s.result
       }
-      case i: IsInvalid => s"${serialize(i.exp)} is invalid${i.info}"
+      case i: IsInvalid => s"${serialize(i.expr)} is invalid${i.info}"
       case s: Stop => s"stop(${serialize(s.clk)}, ${serialize(s.en)}, ${s.ret})${s.info}"
       case p: Print => {
         val q = '"'.toString
@@ -144,7 +144,7 @@ class Serialize {
                       (if (p.args.nonEmpty) p.args.map(serialize).mkString(", ", ", ", "") else "") +
                       s")${p.info}"
       }
-      case s: Empty => "skip"
+      case EmptyStmt => "skip"
       case s: CDefMemory => {
         if (s.seq) s"smem ${s.name} : ${serialize(s.tpe)} [${s.size}]${s.info}"
         else s"cmem ${s.name} : ${serialize(s.tpe)} [${s.size}]${s.info}"
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 408359f0..1308f2c3 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -280,7 +280,7 @@ object Utils extends LazyLogging {
      def getType(): Type = 
        ast match {
          case e: Expression => e.getType
-         case s: Stmt => s.getType
+         case s: Statement => s.getType
          //case f: Field => f.getType
          case t: Type => t.getType
          case p: Port => p.getType
@@ -440,23 +440,22 @@ object Utils extends LazyLogging {
 
 
 // =========== ACCESSORS =========
-   def info (s:Stmt) : Info = {
+   def info (s:Statement) : Info = {
       s match {
          case s:DefWire => s.info
-         case s:DefPoison => s.info
          case s:DefRegister => s.info
          case s:DefInstance => s.info
          case s:WDefInstance => s.info
          case s:DefMemory => s.info
          case s:DefNode => s.info
          case s:Conditionally => s.info
-         case s:BulkConnect => s.info
+         case s:PartialConnect => s.info
          case s:Connect => s.info
          case s:IsInvalid => s.info
          case s:Stop => s.info
          case s:Print => s.info
          case s:Begin => NoInfo
-         case s:Empty => NoInfo
+         case EmptyStmt => NoInfo
       }
    }
    def gender (e:Expression) : Gender = {
@@ -473,21 +472,20 @@ object Utils extends LazyLogging {
         case e:WInvalid => MALE
         case e => println(e); error("Shouldn't be here")
     }}
-   def get_gender (s:Stmt) : Gender =
+   def get_gender (s:Statement) : Gender =
      s match {
        case s:DefWire => BIGENDER
        case s:DefRegister => BIGENDER
        case s:WDefInstance => MALE
        case s:DefNode => MALE
        case s:DefInstance => MALE
-       case s:DefPoison => UNKNOWNGENDER
        case s:DefMemory => MALE
        case s:Begin => UNKNOWNGENDER
        case s:Connect => UNKNOWNGENDER
-       case s:BulkConnect => UNKNOWNGENDER
+       case s:PartialConnect => UNKNOWNGENDER
        case s:Stop => UNKNOWNGENDER
        case s:Print => UNKNOWNGENDER
-       case s:Empty => UNKNOWNGENDER
+       case EmptyStmt => UNKNOWNGENDER
        case s:IsInvalid => UNKNOWNGENDER
      }
    def get_gender (p:Port) : Gender =
@@ -517,10 +515,9 @@ object Utils extends LazyLogging {
          case e:WVoid => UnknownType
          case e:WInvalid => UnknownType
       }
-   def get_type (s:Stmt) : Type = {
+   def get_type (s:Statement) : Type = {
       s match {
        case s:DefWire => s.tpe
-       case s:DefPoison => s.tpe
        case s:DefRegister => s.tpe
        case s:DefNode => tpe(s.value)
        case s:DefMemory => {
@@ -528,11 +525,11 @@ object Utils extends LazyLogging {
           val addr = Field("addr",Default,UIntType(IntWidth(scala.math.max(ceil_log2(depth), 1))))
           val en = Field("en",Default,BoolType())
           val clk = Field("clk",Default,ClockType)
-          val def_data = Field("data",Default,s.data_type)
-          val rev_data = Field("data",Flip,s.data_type)
-          val mask = Field("mask",Default,create_mask(s.data_type))
+          val def_data = Field("data",Default,s.dataType)
+          val rev_data = Field("data",Flip,s.dataType)
+          val mask = Field("mask",Default,create_mask(s.dataType))
           val wmode = Field("wmode",Default,UIntType(IntWidth(1)))
-          val rdata = Field("rdata",Flip,s.data_type)
+          val rdata = Field("rdata",Flip,s.dataType)
           val read_type = BundleType(Seq(rev_data,addr,en,clk))
           val write_type = BundleType(Seq(def_data,mask,addr,en,clk))
           val readwrite_type = BundleType(Seq(wmode,rdata,def_data,mask,addr,en,clk))
@@ -547,10 +544,9 @@ object Utils extends LazyLogging {
        case s:WDefInstance => s.tpe
        case _ => UnknownType
     }}
-   def get_name (s:Stmt) : String = {
+   def get_name (s:Statement) : String = {
       s match {
        case s:DefWire => s.name
-       case s:DefPoison => s.name
        case s:DefRegister => s.name
        case s:DefNode => s.name
        case s:DefMemory => s.name
@@ -558,17 +554,16 @@ object Utils extends LazyLogging {
        case s:WDefInstance => s.name
        case _ => error("Shouldn't be here"); "blah"
     }}
-   def get_info (s:Stmt) : Info = {
+   def get_info (s:Statement) : Info = {
       s match {
        case s:DefWire => s.info
-       case s:DefPoison => s.info
        case s:DefRegister => s.info
        case s:DefInstance => s.info
        case s:WDefInstance => s.info
        case s:DefMemory => s.info
        case s:DefNode => s.info
        case s:Conditionally => s.info
-       case s:BulkConnect => s.info
+       case s:PartialConnect => s.info
        case s:Connect => s.info
        case s:IsInvalid => s.info
        case s:Stop => s.info
@@ -622,7 +617,7 @@ object Utils extends LazyLogging {
     * @throws DeclarationNotFoundException if no declaration of `expr` is found
     */
   def getDeclaration(m: Module, expr: Expression): IsDeclaration = {
-    def getRootDecl(name: String)(s: Stmt): Option[IsDeclaration] = s match {
+    def getRootDecl(name: String)(s: Statement): Option[IsDeclaration] = s match {
       case decl: IsDeclaration => if (decl.name == name) Some(decl) else None
       case c: Conditionally =>
         val m = (getRootDecl(name)(c.conseq), getRootDecl(name)(c.alt))
@@ -657,10 +652,10 @@ object Utils extends LazyLogging {
       def apply_t (t:Type) : Type = t map (apply_t) map (f)
       apply_t(t)
    }
-   def mapr (f: Width => Width, s:Stmt) : Stmt = {
+   def mapr (f: Width => Width, s:Statement) : Statement = {
       def apply_t (t:Type) : Type = mapr(f,t)
       def apply_e (e:Expression) : Expression = e map (apply_e) map (apply_t) map (f)
-      def apply_s (s:Stmt) : Stmt = s map (apply_s) map (apply_e) map (apply_t)
+      def apply_s (s:Statement) : Statement = s map (apply_s) map (apply_e) map (apply_t)
       apply_s(s)
    }
    val ONE = IntWidth(1)
@@ -714,26 +709,25 @@ object Utils extends LazyLogging {
    //   to-stmt(body(m))
    //   map(to-port,ports(m))
    //   sym-hash
-   implicit class StmtUtils(stmt: Stmt) {
+   implicit class StmtUtils(stmt: Statement) {
 
      def getType(): Type =
        stmt match {
          case s: DefWire    => s.tpe
          case s: DefRegister => s.tpe
-         case s: DefMemory  => s.data_type
+         case s: DefMemory  => s.dataType
          case _ => UnknownType
        }
 
      def getInfo: Info =
        stmt match {
          case s: DefWire => s.info
-         case s: DefPoison => s.info
          case s: DefRegister => s.info
          case s: DefInstance => s.info
          case s: DefMemory => s.info
          case s: DefNode => s.info
          case s: Conditionally => s.info
-         case s: BulkConnect => s.info
+         case s: PartialConnect => s.info
          case s: Connect => s.info
          case s: IsInvalid => s.info
          case s: Stop => s.info
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index ff1f9a49..cc4d9c74 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -145,11 +145,11 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
      
 
   // visitBlock
-	private def visitBlock[AST](ctx: FIRRTLParser.BlockContext): Stmt = 
+	private def visitBlock[AST](ctx: FIRRTLParser.BlockContext): Statement =
     Begin(ctx.stmt.map(visitStmt)) 
 
   // Memories are fairly complicated to translate thus have a dedicated method
-  private def visitMem[AST](ctx: FIRRTLParser.StmtContext): Stmt = {
+  private def visitMem[AST](ctx: FIRRTLParser.StmtContext): Statement = {
     def parseChildren(children: Seq[ParseTree], map: Map[String, Seq[ParseTree]]): Map[String, Seq[ParseTree]] = {
       val field = children(0).getText
       if (field == "}") map
@@ -192,7 +192,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
   }
 
   // visitStmt
-	private def visitStmt[AST](ctx: FIRRTLParser.StmtContext): Stmt = {
+  private def visitStmt[AST](ctx: FIRRTLParser.StmtContext): Statement = {
     val info = visitInfo(Option(ctx.info), ctx)
     ctx.getChild(0) match {
       case term: TerminalNode => term.getText match {
@@ -222,19 +222,19 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
         case "inst"  => DefInstance(info, (ctx.id(0).getText), (ctx.id(1).getText))
         case "node" =>  DefNode(info, (ctx.id(0).getText), visitExp(ctx.exp(0)))
         case "when" => {
-          val alt = if (ctx.block.length > 1) visitBlock(ctx.block(1)) else Empty()
+          val alt = if (ctx.block.length > 1) visitBlock(ctx.block(1)) else EmptyStmt
           Conditionally(info, visitExp(ctx.exp(0)), visitBlock(ctx.block(0)), alt)
         }
         case "stop(" => Stop(info, string2Int(ctx.IntLit(0).getText), visitExp(ctx.exp(0)), visitExp(ctx.exp(1)))
         case "printf(" => Print(info, visitStringLit(ctx.StringLit), ctx.exp.drop(2).map(visitExp),
                                 visitExp(ctx.exp(0)), visitExp(ctx.exp(1)))
-        case "skip" => Empty()
+        case "skip" => EmptyStmt
       }
       // If we don't match on the first child, try the next one
       case _ => {
         ctx.getChild(1).getText match {
           case "<=" => Connect(info, visitExp(ctx.exp(0)), visitExp(ctx.exp(1)) )
-          case "<-" => BulkConnect(info, visitExp(ctx.exp(0)), visitExp(ctx.exp(1)) )
+          case "<-" => PartialConnect(info, visitExp(ctx.exp(0)), visitExp(ctx.exp(1)) )
           case "is" => IsInvalid(info, visitExp(ctx.exp(0)))
           case "mport" => CDefMPort(info, ctx.id(0).getText, UnknownType,ctx.id(1).getText,Seq(visitExp(ctx.exp(0)),visitExp(ctx.exp(1))),visitMdir(ctx.mdir))
         }
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index dca1cdff..cdd00e07 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -57,7 +57,7 @@ case class WVoid() extends Expression { def tpe = UnknownType }
 case class WInvalid() extends Expression { def tpe = UnknownType }
 // Useful for splitting then remerging references
 case object EmptyExpression extends Expression { def tpe = UnknownType }
-case class WDefInstance(info:Info,name:String,module:String,tpe:Type) extends Stmt with IsDeclaration
+case class WDefInstance(info:Info,name:String,module:String,tpe:Type) extends Statement with IsDeclaration
 
 // Resultant width is the same as the maximum input width
 case object ADDW_OP extends PrimOp
@@ -227,6 +227,6 @@ case object MRead extends MPortDir
 case object MWrite extends MPortDir
 case object MReadWrite extends MPortDir
 
-case class CDefMemory (val info: Info, val name: String, val tpe: Type, val size: Int, val seq: Boolean) extends Stmt
-case class CDefMPort (val info: Info, val name: String, val tpe: Type, val mem: String, val exps: Seq[Expression], val direction: MPortDir) extends Stmt
+case class CDefMemory (val info: Info, val name: String, val tpe: Type, val size: Int, val seq: Boolean) extends Statement
+case class CDefMPort (val info: Info, val name: String, val tpe: Type, val mem: String, val exps: Seq[Expression], val direction: MPortDir) extends Statement
 
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index 493b7a3a..d364f0dc 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -41,16 +41,16 @@ import annotation.tailrec
 object CheckInitialization extends Pass {
   def name = "Check Initialization"
 
-  private case class VoidExpr(stmt: Stmt, voidDeps: Seq[Expression])
+  private case class VoidExpr(stmt: Statement, voidDeps: Seq[Expression])
 
-  class RefNotInitializedException(info: Info, mname: String, name: String, trace: Seq[Stmt]) extends PassException(
+  class RefNotInitializedException(info: Info, mname: String, name: String, trace: Seq[Statement]) extends PassException(
       s"$info : [module $mname]  Reference $name is not fully initialized.\n" + 
       trace.map(s => s"  ${get_info(s)} : ${s.serialize}").mkString("\n")
     )
 
-  private def getTrace(expr: WrappedExpression, voidExprs: Map[WrappedExpression, VoidExpr]): Seq[Stmt] = {
+  private def getTrace(expr: WrappedExpression, voidExprs: Map[WrappedExpression, VoidExpr]): Seq[Statement] = {
     @tailrec
-    def rec(e: WrappedExpression, map: Map[WrappedExpression, VoidExpr], trace: Seq[Stmt]): Seq[Stmt] = {
+    def rec(e: WrappedExpression, map: Map[WrappedExpression, VoidExpr], trace: Seq[Statement]): Seq[Statement] = {
       val voidExpr = map(e) 
       val newTrace = voidExpr.stmt +: trace
       if (voidExpr.voidDeps.nonEmpty) rec(voidExpr.voidDeps.head, map, newTrace) else newTrace
@@ -85,10 +85,10 @@ object CheckInitialization extends Pass {
         hasVoid(e)
         (void, voidDeps)
       }
-      def checkInitS(s: Stmt): Stmt = {
+      def checkInitS(s: Statement): Statement = {
         s match {
           case con: Connect =>
-            val (hasVoid, voidDeps) = hasVoidExpr(con.exp)
+            val (hasVoid, voidDeps) = hasVoidExpr(con.expr)
             if (hasVoid) voidExprs(con.loc) = VoidExpr(con, voidDeps)
             con
           case node: DefNode =>
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index a88ad051..272c96ea 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -46,7 +46,7 @@ object CheckHighForm extends Pass with LazyLogging {
   // Custom Exceptions
   class NotUniqueException(name: String) extends PassException(s"${sinfo}: [module ${mname}] Reference ${name} does not have a unique name.")
   class InvalidLOCException extends PassException(s"${sinfo}: [module ${mname}] Invalid connect to an expression that is not a reference or a WritePort.")
-  class NegUIntException extends PassException(s"${sinfo}: [module ${mname}] UIntValue cannot be negative.")
+  class NegUIntException extends PassException(s"${sinfo}: [module ${mname}] UIntLiteral cannot be negative.")
   class UndeclaredReferenceException(name: String) extends PassException(s"${sinfo}: [module ${mname}] Reference ${name} is not declared.")
   class PoisonWithFlipException(name: String) extends PassException(s"${sinfo}: [module ${mname}] Poison ${name} cannot be a bundle type with flips.")
   class MemWithFlipException(name: String) extends PassException(s"${sinfo}: [module ${mname}] Memory ${name} cannot be a bundle type with flips.")
@@ -197,7 +197,7 @@ object CheckHighForm extends Pass with LazyLogging {
         e map (checkHighFormT)
         e
       }
-      def checkHighFormS(s: Stmt): Stmt = {
+      def checkHighFormS(s: Statement): Statement = {
         def checkName(name: String): String = {
           if (names.contains(name)) errors.append(new NotUniqueException(name))
           else names(name) = true
@@ -209,12 +209,8 @@ object CheckHighForm extends Pass with LazyLogging {
         s map (checkHighFormT)
         s map (checkHighFormE)
         s match {
-          case s: DefPoison => {
-             if (hasFlip(s.tpe)) errors.append(new PoisonWithFlipException(s.name))
-             checkHighFormT(s.tpe)
-          }
           case s: DefMemory => { 
-            if (hasFlip(s.data_type)) errors.append(new MemWithFlipException(s.name))
+            if (hasFlip(s.dataType)) errors.append(new MemWithFlipException(s.name))
             if (s.depth <= 0) errors.append(new NegMemSizeException)
           }
           case s: WDefInstance => { 
@@ -222,7 +218,7 @@ object CheckHighForm extends Pass with LazyLogging {
               errors.append(new ModuleNotDefinedException(s.module))
           }
           case s: Connect => checkValidLoc(s.loc)
-          case s: BulkConnect => checkValidLoc(s.loc)
+          case s: PartialConnect => checkValidLoc(s.loc)
           case s: Print => checkFstring(s.string, s.args.length)
           case _ => // Do Nothing
         }
@@ -444,11 +440,11 @@ object CheckTypes extends Pass with LazyLogging {
          }
       }
 
-      def check_types_s (s:Stmt) : Stmt = {
+      def check_types_s (s:Statement) : Statement = {
          s map (check_types_e(get_info(s))) match { 
-            case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.exp))) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.exp.serialize))
+            case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.expr))) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.expr.serialize))
             case (s:DefRegister) => if (wt(s.tpe) != wt(tpe(s.init))) errors.append(new InvalidRegInit(s.info))
-            case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp),Default,Default) ) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.exp.serialize))
+            case (s:PartialConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.expr),Default,Default) ) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.expr.serialize))
             case (s:Stop) => {
                if (wt(tpe(s.clk)) != wt(ClockType) ) errors.append(new ReqClk(s.info))
                if (wt(tpe(s.en)) != wt(ut()) ) errors.append(new EnNotUInt(s.info))
@@ -587,12 +583,11 @@ object CheckGenders extends Pass {
          e
       }
         
-      def check_genders_s (genders:HashMap[String,Gender])(s:Stmt) : Stmt = {
+      def check_genders_s (genders:HashMap[String,Gender])(s:Statement) : Statement = {
          s map (check_genders_e(get_info(s),genders))
          s map (check_genders_s(genders))
          (s) match { 
             case (s:DefWire) => genders(s.name) = BIGENDER
-            case (s:DefPoison) => genders(s.name) = MALE
             case (s:DefRegister) => genders(s.name) = BIGENDER
             case (s:DefNode) => {
                check_gender(s.info,genders,MALE)(s.value)
@@ -602,7 +597,7 @@ object CheckGenders extends Pass {
             case (s:WDefInstance) => genders(s.name) = MALE
             case (s:Connect) => {
                check_gender(s.info,genders,FEMALE)(s.loc)
-               check_gender(s.info,genders,MALE)(s.exp)
+               check_gender(s.info,genders,MALE)(s.expr)
             }
             case (s:Print) => {
                for (x <- s.args ) {
@@ -611,14 +606,14 @@ object CheckGenders extends Pass {
                check_gender(s.info,genders,MALE)(s.en)
                check_gender(s.info,genders,MALE)(s.clk)
             }
-            case (s:BulkConnect) => {
+            case (s:PartialConnect) => {
                check_gender(s.info,genders,FEMALE)(s.loc)
-               check_gender(s.info,genders,MALE)(s.exp)
+               check_gender(s.info,genders,MALE)(s.expr)
             }
             case (s:Conditionally) => {
                check_gender(s.info,genders,MALE)(s.pred)
             }
-            case (s:Empty) => false
+            case EmptyStmt => false
             case (s:Stop) => {
                check_gender(s.info,genders,MALE)(s.en)
                check_gender(s.info,genders,MALE)(s.clk)
@@ -687,7 +682,7 @@ object CheckWidths extends Pass {
             }
             e
          }
-         def check_width_s (s:Stmt) : Stmt = {
+         def check_width_s (s:Statement) : Statement = {
             s map (check_width_s) map (check_width_e(get_info(s)))
             def tm (t:Type) : Type = mapr(check_width_w(info(s)) _,t)
             s map (tm)
diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
index 35bd86ce..f58572b1 100644
--- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
+++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
@@ -36,12 +36,12 @@ import annotation.tailrec
 object CommonSubexpressionElimination extends Pass {
   def name = "Common Subexpression Elimination"
 
-  private def cseOnce(s: Stmt): (Stmt, Long) = {
+  private def cseOnce(s: Statement): (Statement, Long) = {
     var nEliminated = 0L
     val expressions = collection.mutable.HashMap[MemoizedHash[Expression], String]()
     val nodes = collection.mutable.HashMap[String, Expression]()
 
-    def recordNodes(s: Stmt): Stmt = s match {
+    def recordNodes(s: Statement): Statement = s match {
       case x: DefNode =>
         nodes(x.name) = x.value
         expressions.getOrElseUpdate(x.value, x.name)
@@ -62,14 +62,14 @@ object CommonSubexpressionElimination extends Pass {
       case _ => e map eliminateNodeRef
     }
 
-    def eliminateNodeRefs(s: Stmt): Stmt = s map eliminateNodeRefs map eliminateNodeRef
+    def eliminateNodeRefs(s: Statement): Statement = s map eliminateNodeRefs map eliminateNodeRef
 
     recordNodes(s)
     (eliminateNodeRefs(s), nEliminated)
   }
 
   @tailrec
-  private def cse(s: Stmt): Stmt = {
+  private def cse(s: Statement): Statement = {
     val (res, n) = cseOnce(s)
     if (n > 0) cse(res) else res
   }
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index 7c78e283..11c14e56 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -132,8 +132,8 @@ object ConstProp extends Pass {
         case _ => false
       }
       def isZero(e: Expression) = e match {
-          case UIntValue(value,_) => value == BigInt(0)
-          case SIntValue(value,_) => value == BigInt(0)
+          case UIntLiteral(value, _) => value == BigInt(0)
+          case SIntLiteral(value, _) => value == BigInt(0)
           case _ => false
         }
       x match {
@@ -159,8 +159,8 @@ object ConstProp extends Pass {
         def <= (that: Range) = this.max <= that.min
       }
       def range(e: Expression): Range = e match {
-        case UIntValue(value, _) => Range(value, value)
-        case SIntValue(value, _) => Range(value, value)
+        case UIntLiteral(value, _) => Range(value, value)
+        case SIntLiteral(value, _) => Range(value, value)
         case _ => tpe(e) match {
           case SIntType(IntWidth(width)) => Range(
             min = BigInt(0) - BigInt(2).pow(width.toInt - 1),
@@ -273,7 +273,7 @@ object ConstProp extends Pass {
       propagated
     }
 
-    def constPropStmt(s: Stmt): Stmt = {
+    def constPropStmt(s: Statement): Statement = {
       s match {
         case x: DefNode => nodeMap(x.name) = x.value
         case _ =>
diff --git a/src/main/scala/firrtl/passes/DeadCodeElimination.scala b/src/main/scala/firrtl/passes/DeadCodeElimination.scala
index cdff1639..8482fe1d 100644
--- a/src/main/scala/firrtl/passes/DeadCodeElimination.scala
+++ b/src/main/scala/firrtl/passes/DeadCodeElimination.scala
@@ -36,7 +36,7 @@ import annotation.tailrec
 object DeadCodeElimination extends Pass {
   def name = "Dead Code Elimination"
 
-  private def dceOnce(s: Stmt): (Stmt, Long) = {
+  private def dceOnce(s: Statement): (Statement, Long) = {
     val referenced = collection.mutable.HashSet[String]()
     var nEliminated = 0L
 
@@ -48,16 +48,16 @@ object DeadCodeElimination extends Pass {
       e
     }
 
-    def checkUse(s: Stmt): Stmt = s map checkUse map checkExpressionUse
+    def checkUse(s: Statement): Statement = s map checkUse map checkExpressionUse
 
-    def maybeEliminate(x: Stmt, name: String) =
+    def maybeEliminate(x: Statement, name: String) =
       if (referenced(name)) x
       else {
         nEliminated += 1
-        Empty()
+        EmptyStmt
       }
 
-    def removeUnused(s: Stmt): Stmt = s match {
+    def removeUnused(s: Statement): Statement = s match {
       case x: DefRegister => maybeEliminate(x, x.name)
       case x: DefWire => maybeEliminate(x, x.name)
       case x: DefNode => maybeEliminate(x, x.name)
@@ -69,7 +69,7 @@ object DeadCodeElimination extends Pass {
   }
 
   @tailrec
-  private def dce(s: Stmt): Stmt = {
+  private def dce(s: Statement): Statement = {
     val (res, n) = dceOnce(s)
     if (n > 0) dce(res) else res
   }
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 1dac5e17..e20ed793 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -70,12 +70,12 @@ object ExpandWhens extends Pass {
     }
     expsx
   }
-  private def squashEmpty(s: Stmt): Stmt = {
+  private def squashEmpty(s: Statement): Statement = {
     s map squashEmpty match {
       case Begin(stmts) =>
-        val newStmts = stmts filter (_ != Empty())
+        val newStmts = stmts filter (_ != EmptyStmt)
         newStmts.size match {
-          case 0 => Empty()
+          case 0 => EmptyStmt
           case 1 => newStmts.head
           case _ => Begin(newStmts)
         }
@@ -102,16 +102,16 @@ object ExpandWhens extends Pass {
 
   // ------------ Pass -------------------
   def run(c: Circuit): Circuit = {
-    def expandWhens(m: Module): (LinkedHashMap[WrappedExpression, Expression], ArrayBuffer[Stmt], Stmt) = {
+    def expandWhens(m: Module): (LinkedHashMap[WrappedExpression, Expression], ArrayBuffer[Statement], Statement) = {
       val namespace = Namespace(m)
-      val simlist = ArrayBuffer[Stmt]()
+      val simlist = ArrayBuffer[Statement]()
 
       // defaults ideally would be immutable.Map but conversion from mutable.LinkedHashMap to mutable.Map is VERY slow
       def expandWhens(
           netlist: LinkedHashMap[WrappedExpression, Expression],
           defaults: Seq[collection.mutable.Map[WrappedExpression, Expression]],
           p: Expression)
-          (s: Stmt): Stmt = {
+          (s: Statement): Statement = {
         s match {
           case w: DefWire =>
             getFemaleRefs(w.name, w.tpe, BIGENDER) foreach (ref => netlist(ref) = WVoid())
@@ -120,13 +120,13 @@ object ExpandWhens extends Pass {
             getFemaleRefs(r.name, r.tpe, BIGENDER) foreach (ref => netlist(ref) = ref)
             r
           case c: Connect =>
-            netlist(c.loc) = c.exp
-            Empty()
+            netlist(c.loc) = c.expr
+            EmptyStmt
           case c: IsInvalid =>
-            netlist(c.exp) = WInvalid()
-            Empty()
+            netlist(c.expr) = WInvalid()
+            EmptyStmt
           case s: Conditionally =>
-            val memos = ArrayBuffer[Stmt]()
+            val memos = ArrayBuffer[Statement]()
 
             val conseqNetlist = LinkedHashMap[WrappedExpression, Expression]()
             val altNetlist = LinkedHashMap[WrappedExpression, Expression]()
@@ -164,14 +164,14 @@ object ExpandWhens extends Pass {
             } else {
               simlist += Print(s.info, s.string, s.args, s.clk, AND(p, s.en))
             }
-            Empty()
+            EmptyStmt
           case s: Stop =>
             if (weq(p, one)) {
               simlist += s
             } else {
               simlist += Stop(s.info, s.ret, s.clk, AND(p, s.en))
             }
-            Empty()
+            EmptyStmt
           case s => s map expandWhens(netlist, defaults, p)
         }
       }
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index f1b71149..d120426b 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -52,7 +52,7 @@ object InlineInstances extends Transform {
          }
       def checkInstance(cn: ComponentName): Unit = {
          var containsCN = false
-         def onStmt(name: String)(s: Stmt): Stmt = {
+         def onStmt(name: String)(s: Statement): Statement = {
             s match {
                case WDefInstance(_, inst_name, module_name, tpe) =>
                   if (name == inst_name) {
@@ -106,7 +106,7 @@ object InlineInstances extends Transform {
             case e => e map onExp
          }
          // Recursive. Inlines tagged instances
-         def onStmt(s: Stmt): Stmt = s match {
+         def onStmt(s: Statement): Statement = s match {
                case WDefInstance(info, instName, moduleName, instTpe) => {
                   def rename(name:String): String = {
                      val newName = instName + inlineDelim + name
@@ -114,7 +114,7 @@ object InlineInstances extends Transform {
                      newName
                   }
                   // Rewrites references in inlined statements from ref to inst$ref
-                  def renameStmt(s: Stmt): Stmt = {
+                  def renameStmt(s: Statement): Statement = {
                      def renameExp(e: Expression): Expression = {
                         e map renameExp match {
                            case WRef(name, tpe, kind, gen) => WRef(rename(name), tpe, kind, gen)
@@ -139,7 +139,7 @@ object InlineInstances extends Transform {
                         case m: ExtModule => throw new PassException("Cannot inline external module")
                         case m: Module => m
                      }
-                     val stmts = mutable.ArrayBuffer[Stmt]()
+                     val stmts = mutable.ArrayBuffer[Statement]()
                      for (p <- instInModule.ports) {
                         stmts += DefWire(p.info, rename(p.name), p.tpe)
                      }
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index 05d46e42..36919756 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -153,7 +153,7 @@ object LowerTypes extends Pass {
         case e: DoPrim => e map (lowerTypesExp)
       }
 
-      def lowerTypesStmt(s: Stmt): Stmt = {
+      def lowerTypesStmt(s: Statement): Statement = {
         s map lowerTypesStmt match {
           case s: DefWire =>
             sinfo = s.info
@@ -195,14 +195,14 @@ object LowerTypes extends Pass {
             }
           case s: DefMemory =>
             sinfo = s.info
-            memDataTypeMap += (s.name -> s.data_type)
-            if (s.data_type.isGround) {
+            memDataTypeMap += (s.name -> s.dataType)
+            if (s.dataType.isGround) {
               s
             } else {
-              val exps = create_exps(s.name, s.data_type)
+              val exps = create_exps(s.name, s.dataType)
               val stmts = exps map { e =>
                 DefMemory(s.info, loweredName(e), tpe(e), s.depth,
-                  s.write_latency, s.read_latency, s.readers, s.writers,
+                  s.writeLatency, s.readLatency, s.readers, s.writers,
                   s.readwriters)
               }
               Begin(stmts)
@@ -224,9 +224,9 @@ object LowerTypes extends Pass {
             Begin(stmts)
           case s: IsInvalid =>
             sinfo = s.info
-            kind(s.exp) match {
+            kind(s.expr) match {
               case k: MemKind =>
-                val exps = lowerTypesMemExp(s.exp)
+                val exps = lowerTypesMemExp(s.expr)
                 Begin(exps map (exp => IsInvalid(s.info, exp)))
               case _ => s map (lowerTypesExp)
             }
@@ -234,7 +234,7 @@ object LowerTypes extends Pass {
             sinfo = s.info
             kind(s.loc) match {
               case k: MemKind =>
-                val exp = lowerTypesExp(s.exp)
+                val exp = lowerTypesExp(s.expr)
                 val locs = lowerTypesMemExp(s.loc)
                 Begin(locs map (loc => Connect(s.info, loc, exp)))
               case _ => s map (lowerTypesExp)
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 58725928..3054aab0 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -57,10 +57,10 @@ object PadWidths extends Pass {
       }
    }
    // Recursive. Fixes assignments and register initialization widths
-   private def onStmt(s: Stmt): Stmt = {
+   private def onStmt(s: Statement): Statement = {
       s map onExp match {
          case s: Connect => {
-            val ex = fixup(width(s.loc))(s.exp)
+            val ex = fixup(width(s.loc))(s.expr)
             Connect(s.info, s.loc, ex)
          }
          case s: DefRegister => {
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 42b51268..094166fb 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -76,7 +76,7 @@ object ToWorkingIR extends Pass {
             case e => e
          }
       }
-      def toStmt (s:Stmt) : Stmt = {
+      def toStmt (s:Statement) : Statement = {
          s map (toExp) match {
             case s:DefInstance => WDefInstance(s.info,s.name,s.module,UnknownType)
             case s => s map (toStmt)
@@ -99,22 +99,21 @@ object ResolveKinds extends Pass {
    def run (c:Circuit): Circuit = {
       def resolve_kinds (m:DefModule, c:Circuit):DefModule = {
          val kinds = LinkedHashMap[String,Kind]()
-         def resolve (body:Stmt) = {
+         def resolve (body:Statement) = {
             def resolve_expr (e:Expression):Expression = {
                e match {
                   case e:WRef => WRef(e.name,tpe(e),kinds(e.name),e.gender)
                   case e => e map (resolve_expr)
                }
             }
-            def resolve_stmt (s:Stmt):Stmt = s map (resolve_stmt) map (resolve_expr)
+            def resolve_stmt (s:Statement):Statement = s map (resolve_stmt) map (resolve_expr)
             resolve_stmt(body)
          }
    
          def find (m:DefModule) = {
-            def find_stmt (s:Stmt):Stmt = {
+            def find_stmt (s:Statement):Statement = {
                s match {
                   case s:DefWire => kinds(s.name) = WireKind()
-                  case s:DefPoison => kinds(s.name) = PoisonKind()
                   case s:DefNode => kinds(s.name) = NodeKind()
                   case s:DefRegister => kinds(s.name) = RegKind()
                   case s:WDefInstance => kinds(s.name) = InstanceKind()
@@ -148,13 +147,12 @@ object ResolveKinds extends Pass {
 object InferTypes extends Pass {
    private var mname = ""
    def name = "Infer Types"
-   def set_type (s:Stmt,t:Type) : Stmt = {
+   def set_type (s:Statement, t:Type) : Statement = {
       s match {
          case s:DefWire => DefWire(s.info,s.name,t)
          case s:DefRegister => DefRegister(s.info,s.name,t,s.clock,s.reset,s.init)
-         case s:DefMemory => DefMemory(s.info,s.name,t,s.depth,s.write_latency,s.read_latency,s.readers,s.writers,s.readwriters)
+         case s:DefMemory => DefMemory(s.info,s.name,t,s.depth,s.writeLatency,s.readLatency,s.readers,s.writers,s.readwriters)
          case s:DefNode => s
-         case s:DefPoison => DefPoison(s.info,s.name,t)
       }
    }
    def remove_unknowns_w (w:Width)(implicit namespace: Namespace):Width = {
@@ -182,7 +180,7 @@ object InferTypes extends Pass {
                case e:SIntValue => e
             }
          }
-         def infer_types_s (s:Stmt) : Stmt = {
+         def infer_types_s (s:Statement) : Statement = {
             s match {
                case s:DefRegister => {
                   val t = remove_unknowns(get_type(s))
@@ -195,12 +193,6 @@ object InferTypes extends Pass {
                   types(s.name) = t
                   set_type(sx,t)
                }
-               case s:DefPoison => {
-                  val sx = s map (infer_types_e)
-                  val t = remove_unknowns(get_type(sx))
-                  types(s.name) = t
-                  set_type(sx,t)
-               }
                case s:DefNode => {
                   val sx = s map (infer_types_e)
                   val t = remove_unknowns(get_type(sx))
@@ -210,7 +202,7 @@ object InferTypes extends Pass {
                case s:DefMemory => {
                   val t = remove_unknowns(get_type(s))
                   types(s.name) = t
-                  val dt = remove_unknowns(s.data_type)
+                  val dt = remove_unknowns(s.dataType)
                   set_type(s,dt)
                }
                case s:WDefInstance => {
@@ -272,21 +264,21 @@ object ResolveGenders extends Pass {
          }
       }
             
-      def resolve_s (s:Stmt) : Stmt = {
+      def resolve_s (s:Statement) : Statement = {
          s match {
             case s:IsInvalid => {
-               val expx = resolve_e(FEMALE)(s.exp)
+               val expx = resolve_e(FEMALE)(s.expr)
                IsInvalid(s.info,expx)
             }
             case s:Connect => {
                val locx = resolve_e(FEMALE)(s.loc)
-               val expx = resolve_e(MALE)(s.exp)
+               val expx = resolve_e(MALE)(s.expr)
                Connect(s.info,locx,expx)
             }
-            case s:BulkConnect => {
+            case s:PartialConnect => {
                val locx = resolve_e(FEMALE)(s.loc)
-               val expx = resolve_e(MALE)(s.exp)
-               BulkConnect(s.info,locx,expx)
+               val expx = resolve_e(MALE)(s.expr)
+               PartialConnect(s.info,locx,expx)
             }
             case s => s map (resolve_e(MALE)) map (resolve_s)
          }
@@ -557,12 +549,12 @@ object InferWidths extends Pass {
                constrain(ONE,width_BANG(e.cond))
                e }
             case (e) => e }}
-      def get_constraints (s:Stmt) : Stmt = {
+      def get_constraints (s:Statement) : Statement = {
          (s map (get_constraints_e)) match {
             case (s:Connect) => {
                val n = get_size(tpe(s.loc))
                val ce_loc = create_exps(s.loc)
-               val ce_exp = create_exps(s.exp)
+               val ce_exp = create_exps(s.expr)
                for (i <- 0 until n) {
                   val locx = ce_loc(i)
                   val expx = ce_exp(i)
@@ -570,11 +562,11 @@ object InferWidths extends Pass {
                      case Default => constrain(width_BANG(locx),width_BANG(expx))
                      case Flip => constrain(width_BANG(expx),width_BANG(locx)) }}
                s }
-            case (s:BulkConnect) => {
-               val ls = get_valid_points(tpe(s.loc),tpe(s.exp),Default,Default)
+            case (s:PartialConnect) => {
+               val ls = get_valid_points(tpe(s.loc),tpe(s.expr),Default,Default)
                for (x <- ls) {
                   val locx = create_exps(s.loc)(x._1)
-                  val expx = create_exps(s.exp)(x._2)
+                  val expx = create_exps(s.expr)(x._2)
                   get_flip(tpe(s.loc),x._1,Default) match {
                      case Default => constrain(width_BANG(locx),width_BANG(expx))
                      case Flip => constrain(width_BANG(expx),width_BANG(locx)) }}
@@ -639,7 +631,7 @@ object PullMuxes extends Pass {
          }
          ex map (pull_muxes_e)
       }
-      def pull_muxes (s:Stmt) : Stmt = s map (pull_muxes) map (pull_muxes_e)
+      def pull_muxes (s:Statement) : Statement = s map (pull_muxes) map (pull_muxes_e)
       val modulesx = c.modules.map {
          m => {
             mname = m.name
@@ -660,7 +652,7 @@ object ExpandConnects extends Pass {
       def expand_connects (m:Module) : Module = {
          mname = m.name
          val genders = LinkedHashMap[String,Gender]()
-         def expand_s (s:Stmt) : Stmt = {
+         def expand_s (s:Statement) : Statement = {
             def set_gender (e:Expression) : Expression = {
                e map (set_gender) match {
                   case (e:WRef) => WRef(e.name,e.tpe,e.kind,genders(e.name))
@@ -679,12 +671,11 @@ object ExpandConnects extends Pass {
                case (s:DefRegister) => { genders(s.name) = BIGENDER; s }
                case (s:WDefInstance) => { genders(s.name) = MALE; s }
                case (s:DefMemory) => { genders(s.name) = MALE; s }
-               case (s:DefPoison) => { genders(s.name) = MALE; s }
                case (s:DefNode) => { genders(s.name) = MALE; s }
                case (s:IsInvalid) => {
-                  val n = get_size(tpe(s.exp))
-                  val invalids = ArrayBuffer[Stmt]()
-                  val exps = create_exps(s.exp)
+                  val n = get_size(tpe(s.expr))
+                  val invalids = ArrayBuffer[Statement]()
+                  val exps = create_exps(s.expr)
                   for (i <- 0 until n) {
                      val expx = exps(i)
                      val gexpx = set_gender(expx)
@@ -695,16 +686,16 @@ object ExpandConnects extends Pass {
                      }
                   }
                   if (invalids.length == 0) {
-                     Empty()
+                     EmptyStmt
                   } else if (invalids.length == 1) {
                      invalids(0)
                   } else Begin(invalids)
                }
                case (s:Connect) => {
                   val n = get_size(tpe(s.loc))
-                  val connects = ArrayBuffer[Stmt]()
+                  val connects = ArrayBuffer[Statement]()
                   val locs = create_exps(s.loc)
-                  val exps = create_exps(s.exp)
+                  val exps = create_exps(s.expr)
                   for (i <- 0 until n) {
                      val locx = locs(i)
                      val expx = exps(i)
@@ -716,11 +707,11 @@ object ExpandConnects extends Pass {
                   }
                   Begin(connects)
                }
-               case (s:BulkConnect) => {
-                  val ls = get_valid_points(tpe(s.loc),tpe(s.exp),Default,Default)
-                  val connects = ArrayBuffer[Stmt]()
+               case (s:PartialConnect) => {
+                  val ls = get_valid_points(tpe(s.loc),tpe(s.expr),Default,Default)
+                  val connects = ArrayBuffer[Statement]()
                   val locs = create_exps(s.loc)
-                  val exps = create_exps(s.exp)
+                  val exps = create_exps(s.expr)
                   ls.foreach { x => {
                      val locx = locs(x._1)
                      val expx = exps(x._2)
@@ -819,8 +810,8 @@ object RemoveAccesses extends Pass {
       def remove_m (m:Module) : Module = {
          val namespace = Namespace(m)
          mname = m.name
-         def remove_s (s:Stmt) : Stmt = {
-            val stmts = ArrayBuffer[Stmt]()
+         def remove_s (s:Statement) : Statement = {
+            val stmts = ArrayBuffer[Statement]()
             def create_temp (e:Expression) : Expression = {
                val n = namespace.newTemp
                stmts += DefWire(info(s),n,tpe(e))
@@ -852,7 +843,7 @@ object RemoveAccesses extends Pass {
                                     if (i < temps.size) {
                                        stmts += Connect(info(s),get_temp(i),x.base)
                                     } else {
-                                       stmts += Conditionally(info(s),x.guard,Connect(info(s),get_temp(i),x.base),Empty())
+                                       stmts += Conditionally(info(s),x.guard,Connect(info(s),get_temp(i),x.base),EmptyStmt)
                                     }
                                  }
                               }
@@ -872,11 +863,11 @@ object RemoveAccesses extends Pass {
                         if (ls.size == 1 & weq(ls(0).guard,one)) s.loc
                         else {
                            val temp = create_temp(s.loc)
-                           for (x <- ls) { stmts += Conditionally(s.info,x.guard,Connect(s.info,x.base,temp),Empty()) }
+                           for (x <- ls) { stmts += Conditionally(s.info,x.guard,Connect(s.info,x.base,temp),EmptyStmt) }
                            temp
                         }
-                     Connect(s.info,locx,remove_e(s.exp))
-                  } else { Connect(s.info,s.loc,remove_e(s.exp)) }
+                     Connect(s.info,locx,remove_e(s.expr))
+                  } else { Connect(s.info,s.loc,remove_e(s.expr)) }
                }
                case (s) => s map (remove_e) map (remove_s)
             }
@@ -920,16 +911,16 @@ object Legalize extends Pass {
     }
     case _ => e
   }
-  def legalizeConnect(c: Connect): Stmt = {
+  def legalizeConnect(c: Connect): Statement = {
     val t = tpe(c.loc)
     val w = long_BANG(t)
-    if (w >= long_BANG(tpe(c.exp))) c
+    if (w >= long_BANG(tpe(c.expr))) c
     else {
       val newType = t match {
         case _: UIntType => UIntType(IntWidth(w))
         case _: SIntType => SIntType(IntWidth(w))
       }
-      Connect(c.info, c.loc, DoPrim(BITS_SELECT_OP, Seq(c.exp), Seq(w-1, 0), newType))
+      Connect(c.info, c.loc, DoPrim(BITS_SELECT_OP, Seq(c.expr), Seq(w-1, 0), newType))
     }
   }
   def run (c: Circuit): Circuit = {
@@ -939,7 +930,7 @@ object Legalize extends Pass {
         case e => e
       }
     }
-    def legalizeS (s: Stmt): Stmt = {
+    def legalizeS (s: Statement): Statement = {
       val legalizedStmt = s match {
         case c: Connect => legalizeConnect(c)
         case _ => s
@@ -973,7 +964,7 @@ object VerilogWrap extends Pass {
          case (e) => e
       }
    }
-   def v_wrap_s (s:Stmt) : Stmt = {
+   def v_wrap_s (s:Statement) : Statement = {
       s map (v_wrap_s) map (v_wrap_e) match {
         case s: Print =>
            Print(s.info, VerilogStringLitHandler.format(s.string), s.args, s.clk, s.en)
@@ -1006,7 +997,7 @@ object VerilogRename extends Pass {
            case (e) => e map (verilog_rename_e)
          }
       }
-      def verilog_rename_s (s:Stmt) : Stmt = {
+      def verilog_rename_s (s:Statement) : Statement = {
         s map (verilog_rename_s) map (verilog_rename_e) map (verilog_rename_n)
       }
       val modulesx = c.modules.map{ m => {
@@ -1025,14 +1016,13 @@ object VerilogRename extends Pass {
 object CInferTypes extends Pass {
    def name = "CInfer Types"
    var mname = ""
-   def set_type (s:Stmt,t:Type) : Stmt = {
+   def set_type (s:Statement, t:Type) : Statement = {
       (s) match { 
          case (s:DefWire) => DefWire(s.info,s.name,t)
          case (s:DefRegister) => DefRegister(s.info,s.name,t,s.clock,s.reset,s.init)
          case (s:CDefMemory) => CDefMemory(s.info,s.name,t,s.size,s.seq)
          case (s:CDefMPort) => CDefMPort(s.info,s.name,t,s.mem,s.exps,s.direction)
          case (s:DefNode) => s
-         case (s:DefPoison) => DefPoison(s.info,s.name,t)
       }
    }
    
@@ -1073,7 +1063,7 @@ object CInferTypes extends Pass {
                case (_:UIntValue|_:SIntValue) => e
             }
          }
-         def infer_types_s (s:Stmt) : Stmt = {
+         def infer_types_s (s:Statement) : Statement = {
             (s) match { 
                case (s:DefRegister) => {
                   types(s.name) = s.tpe
@@ -1084,10 +1074,6 @@ object CInferTypes extends Pass {
                   types(s.name) = s.tpe
                   s
                }
-               case (s:DefPoison) => {
-                  types(s.name) = s.tpe
-                  s
-               }
                case (s:DefNode) => {
                   val sx = s map (infer_types_e)
                   val t = get_type(sx)
@@ -1169,26 +1155,26 @@ object CInferMDir extends Pass {
                case (e) => e
             }
          }
-         def infer_mdir_s (s:Stmt) : Stmt = {
+         def infer_mdir_s (s:Statement) : Statement = {
             (s) match { 
                case (s:CDefMPort) => {
                   mports(s.name) = s.direction
                   s map (infer_mdir_e(MRead))
                }
                case (s:Connect) => {
-                  infer_mdir_e(MRead)(s.exp)
+                  infer_mdir_e(MRead)(s.expr)
                   infer_mdir_e(MWrite)(s.loc)
                   s
                }
-               case (s:BulkConnect) => {
-                  infer_mdir_e(MRead)(s.exp)
+               case (s:PartialConnect) => {
+                  infer_mdir_e(MRead)(s.expr)
                   infer_mdir_e(MWrite)(s.loc)
                   s
                }
                case (s) => s map (infer_mdir_s) map (infer_mdir_e(MRead))
             }
          }
-         def set_mdir_s (s:Stmt) : Stmt = {
+         def set_mdir_s (s:Statement) : Statement = {
             (s) match { 
                case (s:CDefMPort) => 
                   CDefMPort(s.info,s.name,s.tpe,s.mem,s.exps,mports(s.name))
@@ -1243,7 +1229,7 @@ object RemoveCHIRRTL extends Pass {
          val ut = UnknownType
          val mport_types = LinkedHashMap[String,Type]()
          def EMPs () : MPorts = MPorts(ArrayBuffer[MPort](),ArrayBuffer[MPort](),ArrayBuffer[MPort]())
-         def collect_mports (s:Stmt) : Stmt = {
+         def collect_mports (s:Statement) : Statement = {
             (s) match { 
                case (s:CDefMPort) => {
                   val mports = hash.getOrElse(s.mem,EMPs())
@@ -1258,11 +1244,11 @@ object RemoveCHIRRTL extends Pass {
                case (s) => s map (collect_mports)
             }
          }
-         def collect_refs (s:Stmt) : Stmt = {
+         def collect_refs (s:Statement) : Statement = {
             (s) match { 
                case (s:CDefMemory) => {
                   mport_types(s.name) = s.tpe
-                  val stmts = ArrayBuffer[Stmt]()
+                  val stmts = ArrayBuffer[Statement]()
                   val taddr = UIntType(IntWidth(scala.math.max(1,ceil_log2(s.size))))
                   val tdata = s.tpe
                   def set_poison (vec:Seq[MPort],addr:String) : Unit = {
@@ -1330,7 +1316,7 @@ object RemoveCHIRRTL extends Pass {
                         ens += "en"
                      }
                   }
-                  val stmts = ArrayBuffer[Stmt]()
+                  val stmts = ArrayBuffer[Statement]()
                   for (x <- addrs ) {
                      stmts += Connect(s.info,SubField(SubField(Ref(s.mem,ut),s.name,ut),x,ut),s.exps(0))
                   }
@@ -1345,7 +1331,7 @@ object RemoveCHIRRTL extends Pass {
                case (s) => s map (collect_refs)
             }
          }
-         def remove_chirrtl_s (s:Stmt) : Stmt = {
+         def remove_chirrtl_s (s:Statement) : Statement = {
             var has_write_mport = false
             var has_readwrite_mport:Option[Expression] = None
             def remove_chirrtl_e (g:Gender)(e:Expression) : Expression = {
@@ -1382,8 +1368,8 @@ object RemoveCHIRRTL extends Pass {
             }
             (s) match { 
                case (s:Connect) => {
-                  val stmts = ArrayBuffer[Stmt]()
-                  val rocx = remove_chirrtl_e(MALE)(s.exp)
+                  val stmts = ArrayBuffer[Statement]()
+                  val rocx = remove_chirrtl_e(MALE)(s.expr)
                   val locx = remove_chirrtl_e(FEMALE)(s.loc)
                   stmts += Connect(s.info,locx,rocx)
                   if (has_write_mport) {
@@ -1399,13 +1385,13 @@ object RemoveCHIRRTL extends Pass {
                   if (stmts.size > 1) Begin(stmts)
                   else stmts(0)
                }
-               case (s:BulkConnect) => {
-                  val stmts = ArrayBuffer[Stmt]()
+               case (s:PartialConnect) => {
+                  val stmts = ArrayBuffer[Statement]()
                   val locx = remove_chirrtl_e(FEMALE)(s.loc)
-                  val rocx = remove_chirrtl_e(MALE)(s.exp)
-                  stmts += BulkConnect(s.info,locx,rocx)
+                  val rocx = remove_chirrtl_e(MALE)(s.expr)
+                  stmts += PartialConnect(s.info,locx,rocx)
                   if (has_write_mport != false) {
-                     val ls = get_valid_points(tpe(s.loc),tpe(s.exp),Default,Default)
+                     val ls = get_valid_points(tpe(s.loc),tpe(s.expr),Default,Default)
                      val locs = create_exps(get_mask(s.loc))
                      for (x <- ls ) {
                         val locx = locs(x._1)
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
index 5117caaf..486e9ff8 100644
--- a/src/main/scala/firrtl/passes/RemoveValidIf.scala
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -13,7 +13,7 @@ object RemoveValidIf extends Pass {
       }
    }
    // Recursive.
-   private def onStmt(s: Stmt): Stmt = s map onStmt map onExp
+   private def onStmt(s: Statement): Statement = s map onStmt map onExp
 
    private def onModule(m: DefModule): DefModule = {
       m match {
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala
index 4f7fa208..61f01e01 100644
--- a/src/main/scala/firrtl/passes/SplitExpressions.scala
+++ b/src/main/scala/firrtl/passes/SplitExpressions.scala
@@ -12,8 +12,8 @@ object SplitExpressions extends Pass {
    def name = "Split Expressions"
    private def onModule(m: Module): Module = {
       val namespace = Namespace(m)
-      def onStmt(s: Stmt): Stmt = {
-         val v = mutable.ArrayBuffer[Stmt]()
+      def onStmt(s: Statement): Statement = {
+         val v = mutable.ArrayBuffer[Statement]()
          // Splits current expression if needed
          // Adds named temporaries to v
          def split(e: Expression): Expression = e match {
@@ -45,7 +45,7 @@ object SplitExpressions extends Pass {
          val x = s map onExp
          x match {
             case x: Begin => x map onStmt
-            case x: Empty => x
+            case EmptyStmt => x
             case x => {
                v += x
                if (v.size > 1) Begin(v.toVector)
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index d0442f37..2fdc3454 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -220,24 +220,24 @@ object Uniquify extends Pass {
   }
 
   // Creates a Bundle Type from a Stmt
-  def stmtToType(s: Stmt)(implicit sinfo: Info, mname: String): BundleType = {
+  def stmtToType(s: Statement)(implicit sinfo: Info, mname: String): BundleType = {
     // Recursive helper
-    def recStmtToType(s: Stmt): Seq[Field] = s match {
+    def recStmtToType(s: Statement): Seq[Field] = s match {
       case s: DefWire => Seq(Field(s.name, Default, s.tpe))
       case s: DefRegister => Seq(Field(s.name, Default, s.tpe))
       case s: WDefInstance => Seq(Field(s.name, Default, s.tpe))
-      case s: DefMemory => s.data_type match {
+      case s: DefMemory => s.dataType match {
         case (_: UIntType | _: SIntType) =>
           Seq(Field(s.name, Default, get_type(s)))
         case tpe: BundleType =>
           val newFields = tpe.fields map ( f =>
-            DefMemory(s.info, f.name, f.tpe, s.depth, s.write_latency,
-              s.read_latency, s.readers, s.writers, s.readwriters)
+            DefMemory(s.info, f.name, f.tpe, s.depth, s.writeLatency,
+              s.readLatency, s.readers, s.writers, s.readwriters)
           ) flatMap (recStmtToType)
           Seq(Field(s.name, Default, BundleType(newFields)))
         case tpe: VectorType =>
           val newFields = (0 until tpe.size) map ( i =>
-            s.copy(name = i.toString, data_type = tpe.tpe)
+            s.copy(name = i.toString, dataType = tpe.tpe)
           ) flatMap (recStmtToType)
           Seq(Field(s.name, Default, BundleType(newFields)))
       }
@@ -271,7 +271,7 @@ object Uniquify extends Pass {
         case e: DoPrim => e map (uniquifyExp)
       }
 
-      def uniquifyStmt(s: Stmt): Stmt = {
+      def uniquifyStmt(s: Statement): Statement = {
         s map uniquifyStmt map uniquifyExp match {
           case s: DefWire =>
             sinfo = s.info
@@ -302,8 +302,8 @@ object Uniquify extends Pass {
             sinfo = s.info
             if (nameMap.contains(s.name)) {
               val node = nameMap(s.name)
-              val dataType = uniquifyNamesType(s.data_type, node.elts)
-              val mem = s.copy(name = node.name, data_type = dataType)
+              val dataType = uniquifyNamesType(s.dataType, node.elts)
+              val mem = s.copy(name = node.name, dataType = dataType)
               // Create new mapping to handle references to memory data fields
               val uniqueMemMap = createNameMapping(get_type(s), get_type(mem))
               nameMap(s.name) = NameMapNode(node.name, node.elts ++ uniqueMemMap)
@@ -323,7 +323,7 @@ object Uniquify extends Pass {
         }
       }
 
-      def uniquifyBody(s: Stmt): Stmt = {
+      def uniquifyBody(s: Statement): Statement = {
         val bodyType = stmtToType(s)
         val uniqueBodyType = uniquifyNames(bodyType, namespace)
         val localMap = createNameMapping(bodyType, uniqueBodyType)