diff options
| author | Adam Izraelevitz | 2016-04-27 13:32:04 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-05-10 14:48:18 -0700 |
| commit | e08c8c0b82cc68cf8d635ff9446e8d8106c4d867 (patch) | |
| tree | 133090b8a510edc61be7b656d8056a29bdefd9c0 /src | |
| parent | 5fe29442a9b22eb97c096cd3e8416b7a057718e9 (diff) | |
Modified Verilog compiler to use new passes
RemoveValidIf, SplitExpressions, and PadWidths
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index cf2fc43d..08ff421f 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -86,11 +86,13 @@ object VerilogCompiler extends Compiler { InferTypes, ResolveGenders, InferWidths, - SplitExp, + RemoveValidIf, ConstProp, + PadWidths, + VerilogWrap, + SplitExpressions, CommonSubexpressionElimination, DeadCodeElimination, - VerilogWrap, VerilogRename ) def run(c: Circuit, w: Writer) |