diff options
| author | Adam Izraelevitz | 2016-04-27 13:31:35 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-05-10 14:44:53 -0700 |
| commit | 5fe29442a9b22eb97c096cd3e8416b7a057718e9 (patch) | |
| tree | 3e87b385a379d3586eff89b879d6ad9f475a4ff3 /src | |
| parent | e78b2b277a93d7d635036da559def6189a2047a2 (diff) | |
Added RemoveValidIf pass.
This is to start moving stuff out of Emitter and into separate passes
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/RemoveValidIf.scala | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala new file mode 100644 index 00000000..4bc6162a --- /dev/null +++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala @@ -0,0 +1,26 @@ +package firrtl +package passes +import firrtl.Mappers.{ExpMap, StmtMap} + +// Removes ValidIf as an optimization +object RemoveValidIf extends Pass { + def name = "Remove ValidIfs" + // Recursive. Removes ValidIf's + private def onExp(e: Expression): Expression = { + e map onExp match { + case ValidIf(cond, value, tpe) => value + case x => x + } + } + // Recursive. + private def onStmt(s: Stmt): Stmt = s map onStmt map onExp + + private def onModule(m: Module): Module = { + m match { + case m:InModule => InModule(m.info, m.name, m.ports, onStmt(m.body)) + case m:ExModule => m + } + } + + def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule _), c.main) +} |
