From 5fe29442a9b22eb97c096cd3e8416b7a057718e9 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Wed, 27 Apr 2016 13:31:35 -0700
Subject: Added RemoveValidIf pass.

This is to start moving stuff out of Emitter and into separate passes
---
 src/main/scala/firrtl/passes/RemoveValidIf.scala | 26 ++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 src/main/scala/firrtl/passes/RemoveValidIf.scala

(limited to 'src')

diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
new file mode 100644
index 00000000..4bc6162a
--- /dev/null
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -0,0 +1,26 @@
+package firrtl
+package passes
+import firrtl.Mappers.{ExpMap, StmtMap}
+
+// Removes ValidIf as an optimization
+object RemoveValidIf extends Pass {
+   def name = "Remove ValidIfs"
+   // Recursive. Removes ValidIf's
+   private def onExp(e: Expression): Expression = {
+      e map onExp match {
+         case ValidIf(cond, value, tpe) => value
+         case x => x
+      }
+   }
+   // Recursive.
+   private def onStmt(s: Stmt): Stmt = s map onStmt map onExp
+
+   private def onModule(m: Module): Module = {
+      m match {
+         case m:InModule => InModule(m.info, m.name, m.ports, onStmt(m.body))
+         case m:ExModule => m
+      }
+   }
+
+   def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule _), c.main)
+}
-- 
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