From e08c8c0b82cc68cf8d635ff9446e8d8106c4d867 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Wed, 27 Apr 2016 13:32:04 -0700
Subject: Modified Verilog compiler to use new passes

RemoveValidIf, SplitExpressions, and PadWidths
---
 src/main/scala/firrtl/Compiler.scala | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala
index cf2fc43d..08ff421f 100644
--- a/src/main/scala/firrtl/Compiler.scala
+++ b/src/main/scala/firrtl/Compiler.scala
@@ -86,11 +86,13 @@ object VerilogCompiler extends Compiler {
     InferTypes,
     ResolveGenders,
     InferWidths,
-    SplitExp,
+    RemoveValidIf,
     ConstProp,
+    PadWidths,
+    VerilogWrap,
+    SplitExpressions,
     CommonSubexpressionElimination,
     DeadCodeElimination,
-    VerilogWrap,
     VerilogRename
   )
   def run(c: Circuit, w: Writer)
-- 
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