API Cleanup - Type

trait Type -> abstract class Type
case class ClockType() -> case object ClockType
case class UnknownType() -> case object UnknownType
Add GroundType and AggregateType
ClockType has width of IntWidth(1)

10 files changed, 105 insertions, 103 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 2b19f24e..1455b912 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -76,7 +76,7 @@ class VerilogEmitter extends Emitter {
          e.tpe match {
             case (t:UIntType) => e
             case (t:SIntType) => Seq("$signed(",e,")")
-            case (t:ClockType) => e
+            case ClockType => e
          }
       }
       (x) match {
@@ -99,7 +99,7 @@ class VerilogEmitter extends Emitter {
                case (_:UIntType|_:SIntType) => 
                   val wx = long_BANG(t) - 1
                   if (wx > 0) w.get.write("[" + wx + ":0]") else w.get.write("")
-               case (t:ClockType) => w.get.write("")
+               case ClockType => w.get.write("")
                case (t:VectorType) => 
                   emit2(t.tpe, top + 1)
                   w.get.write("[" + (t.size - 1) + ":0]")
@@ -511,8 +511,8 @@ class VerilogEmitter extends Emitter {
                   val enx = delay(en,s.read_latency,clk)
                   val mem_port = WSubAccess(mem,addrx,s.data_type,UNKNOWNGENDER)
                   val depthValue = UIntValue(s.depth, IntWidth(BigInt(s.depth).bitLength))
-                  val garbageGuard = DoPrim(GREATER_EQ_OP, Seq(addrx, depthValue), Seq(), UnknownType())
-                  val garbageMux = Mux(garbageGuard, VRandom, mem_port, UnknownType())
+                  val garbageGuard = DoPrim(GREATER_EQ_OP, Seq(addrx, depthValue), Seq(), UnknownType)
+                  val garbageMux = Mux(garbageGuard, VRandom, mem_port, UnknownType)
                   synSimAssign(data, mem_port, garbageMux)
                }
    
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index d9dab2d9..08be0fe8 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -153,13 +153,19 @@ case object REVERSE extends Flip
 
 case class Field(name: String, flip: Flip, tpe: Type) extends AST with HasName
 
-trait Type extends AST
-case class UIntType(width: Width) extends Type
-case class SIntType(width: Width) extends Type
-case class BundleType(fields: Seq[Field]) extends Type
-case class VectorType(tpe: Type, size: Int) extends Type
-case class ClockType() extends Type
-case class UnknownType() extends Type
+abstract class Type extends AST
+abstract class GroundType extends Type {
+  val width: Width
+}
+abstract class AggregateType extends Type
+case class UIntType(width: Width) extends GroundType
+case class SIntType(width: Width) extends GroundType
+case class BundleType(fields: Seq[Field]) extends AggregateType
+case class VectorType(tpe: Type, size: Int) extends AggregateType
+case object ClockType extends GroundType {
+  val width = IntWidth(1)
+}
+case object UnknownType extends Type
 
 /** [[Port]] Direction */
 abstract class Direction extends AST
diff --git a/src/main/scala/firrtl/PrimOps.scala b/src/main/scala/firrtl/PrimOps.scala
index ed3752f9..5025f3a6 100644
--- a/src/main/scala/firrtl/PrimOps.scala
+++ b/src/main/scala/firrtl/PrimOps.scala
@@ -105,7 +105,7 @@ object PrimOps extends LazyLogging {
                case (t1:UIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
                case (t1:SIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
                case (t1:SIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -115,7 +115,7 @@ object PrimOps extends LazyLogging {
                case (t1:UIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
                case (t1:SIntType, t2:UIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
                case (t1:SIntType, t2:SIntType) => SIntType(PLUS(MAX(w1(),w2()),ONE))
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -125,7 +125,7 @@ object PrimOps extends LazyLogging {
                case (t1:UIntType, t2:SIntType) => SIntType(PLUS(w1(),w2()))
                case (t1:SIntType, t2:UIntType) => SIntType(PLUS(w1(),w2()))
                case (t1:SIntType, t2:SIntType) => SIntType(PLUS(w1(),w2()))
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -135,7 +135,7 @@ object PrimOps extends LazyLogging {
                case (t1:UIntType, t2:SIntType) => SIntType(PLUS(w1(),ONE))
                case (t1:SIntType, t2:UIntType) => SIntType(w1())
                case (t1:SIntType, t2:SIntType) => SIntType(PLUS(w1(),ONE))
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -145,7 +145,7 @@ object PrimOps extends LazyLogging {
                case (t1:UIntType, t2:SIntType) => UIntType(MIN(w1(),w2()))
                case (t1:SIntType, t2:UIntType) => SIntType(MIN(w1(),PLUS(w2(),ONE)))
                case (t1:SIntType, t2:SIntType) => SIntType(MIN(w1(),w2()))
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -155,7 +155,7 @@ object PrimOps extends LazyLogging {
                case (t1:SIntType, t2:UIntType) => BoolType()
                case (t1:UIntType, t2:SIntType) => BoolType()
                case (t1:SIntType, t2:SIntType) => BoolType()
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -165,7 +165,7 @@ object PrimOps extends LazyLogging {
                case (t1:SIntType, t2:UIntType) => BoolType()
                case (t1:UIntType, t2:SIntType) => BoolType()
                case (t1:SIntType, t2:SIntType) => BoolType()
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -175,7 +175,7 @@ object PrimOps extends LazyLogging {
                case (t1:SIntType, t2:UIntType) => BoolType()
                case (t1:UIntType, t2:SIntType) => BoolType()
                case (t1:SIntType, t2:SIntType) => BoolType()
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -185,7 +185,7 @@ object PrimOps extends LazyLogging {
                case (t1:SIntType, t2:UIntType) => BoolType()
                case (t1:UIntType, t2:SIntType) => BoolType()
                case (t1:SIntType, t2:SIntType) => BoolType()
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -195,7 +195,7 @@ object PrimOps extends LazyLogging {
                case (t1:SIntType, t2:UIntType) => BoolType()
                case (t1:UIntType, t2:SIntType) => BoolType()
                case (t1:SIntType, t2:SIntType) => BoolType()
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -205,7 +205,7 @@ object PrimOps extends LazyLogging {
                case (t1:SIntType, t2:UIntType) => BoolType()
                case (t1:UIntType, t2:SIntType) => BoolType()
                case (t1:SIntType, t2:SIntType) => BoolType()
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -213,7 +213,7 @@ object PrimOps extends LazyLogging {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(MAX(w1(),c1()))
                case (t1:SIntType) => SIntType(MAX(w1(),c1()))
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -221,8 +221,8 @@ object PrimOps extends LazyLogging {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(w1())
                case (t1:SIntType) => UIntType(w1())
-               case (t1:ClockType) => UIntType(ONE)
-               case (t1) => UnknownType()
+               case ClockType => UIntType(ONE)
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -230,17 +230,17 @@ object PrimOps extends LazyLogging {
             val t = (t1()) match {
                case (t1:UIntType) => SIntType(w1())
                case (t1:SIntType) => SIntType(w1())
-               case (t1:ClockType) => SIntType(ONE)
-               case (t1) => UnknownType()
+               case ClockType => SIntType(ONE)
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case AS_CLOCK_OP => {
             val t = (t1()) match {
-               case (t1:UIntType) => ClockType()
-               case (t1:SIntType) => ClockType()
-               case (t1:ClockType) => ClockType()
-               case (t1) => UnknownType()
+               case (t1:UIntType) => ClockType
+               case (t1:SIntType) => ClockType
+               case ClockType => ClockType
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -248,7 +248,7 @@ object PrimOps extends LazyLogging {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(PLUS(w1(),c1()))
                case (t1:SIntType) => SIntType(PLUS(w1(),c1()))
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -256,7 +256,7 @@ object PrimOps extends LazyLogging {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(MAX(MINUS(w1(),c1()),ONE))
                case (t1:SIntType) => SIntType(MAX(MINUS(w1(),c1()),ONE))
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -264,7 +264,7 @@ object PrimOps extends LazyLogging {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(PLUS(w1(),POW(w2())))
                case (t1:SIntType) => SIntType(PLUS(w1(),POW(w2())))
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -272,7 +272,7 @@ object PrimOps extends LazyLogging {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(w1())
                case (t1:SIntType) => SIntType(w1())
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -280,7 +280,7 @@ object PrimOps extends LazyLogging {
             val t = (t1()) match {
                case (t1:UIntType) => SIntType(PLUS(w1(),ONE))
                case (t1:SIntType) => SIntType(w1())
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -288,7 +288,7 @@ object PrimOps extends LazyLogging {
             val t = (t1()) match {
                case (t1:UIntType) => SIntType(PLUS(w1(),ONE))
                case (t1:SIntType) => SIntType(PLUS(w1(),ONE))
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
@@ -296,77 +296,77 @@ object PrimOps extends LazyLogging {
             val t = (t1()) match {
                case (t1:UIntType) => UIntType(w1())
                case (t1:SIntType) => UIntType(w1())
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case AND_OP => {
             val t = (t1(),t2()) match {
                case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2()))
-               case (t1,t2) => UnknownType()
+               case (t1,t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case OR_OP => {
             val t = (t1(),t2()) match {
                case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2()))
-               case (t1,t2) => UnknownType()
+               case (t1,t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case XOR_OP => {
             val t = (t1(),t2()) match {
                case (_:SIntType|_:UIntType, _:SIntType|_:UIntType) => UIntType(MAX(w1(),w2()))
-               case (t1,t2) => UnknownType()
+               case (t1,t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case AND_REDUCE_OP => {
             val t = (t1()) match {
                case (_:UIntType|_:SIntType) => BoolType()
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case OR_REDUCE_OP => {
             val t = (t1()) match {
                case (_:UIntType|_:SIntType) => BoolType()
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case XOR_REDUCE_OP => {
             val t = (t1()) match {
                case (_:UIntType|_:SIntType) => BoolType()
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case CONCAT_OP => {
             val t = (t1(),t2()) match {
                case (_:UIntType|_:SIntType,_:UIntType|_:SIntType) => UIntType(PLUS(w1(),w2()))
-               case (t1, t2) => UnknownType()
+               case (t1, t2) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case BITS_SELECT_OP => {
             val t = (t1()) match {
                case (_:UIntType|_:SIntType) => UIntType(PLUS(MINUS(c1(),c2()),ONE))
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case HEAD_OP => {
             val t = (t1()) match {
                case (_:UIntType|_:SIntType) => UIntType(c1())
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
          case TAIL_OP => {
             val t = (t1()) match {
                case (_:UIntType|_:SIntType) => UIntType(MINUS(w1(),c1()))
-               case (t1) => UnknownType()
+               case (t1) => UnknownType
             }
             DoPrim(o,a,c,t)
          }
diff --git a/src/main/scala/firrtl/Serialize.scala b/src/main/scala/firrtl/Serialize.scala
index 5a5b690d..e46ce111 100644
--- a/src/main/scala/firrtl/Serialize.scala
+++ b/src/main/scala/firrtl/Serialize.scala
@@ -182,8 +182,8 @@ class Serialize {
   def serialize(t: Type): String = {
     val commas = ", " // for mkString in BundleType
     t match {
-      case c:ClockType => "Clock"
-      case u:UnknownType => "?"
+      case ClockType => "Clock"
+      case UnknownType => "?"
       case t: UIntType => s"UInt${serialize(t.width)}"
       case t: SIntType => s"SInt${serialize(t.width)}"
       case t: BundleType => s"{ ${t.fields.map(serialize).mkString(commas)}}"
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 9c0a59cb..a85dedb5 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -136,7 +136,7 @@ object Utils extends LazyLogging {
             tpe(e) match {
                case (t:UIntType) => Seq(e)
                case (t:SIntType) => Seq(e)
-               case (t:ClockType) => Seq(e)
+               case ClockType => Seq(e)
                case (t:BundleType) => {
                   t.fields.flatMap { f => create_exps(WSubField(e,f.name,f.tpe,times(gender(e), f.flip))) }
                }
@@ -152,7 +152,7 @@ object Utils extends LazyLogging {
       val x = t match {
          case (t:UIntType) => f
          case (t:SIntType) => f
-         case (t:ClockType) => f
+         case ClockType => f
          case (t:BundleType) => {
             var n = i
             var ret:Option[Flip] = None
@@ -212,7 +212,7 @@ object Utils extends LazyLogging {
                   Field(f1.name,f1.flip,mux_type(f1.tpe,f2.tpe))
                }))
          }
-      } else UnknownType()
+      } else UnknownType
    }
    def mux_type_and_widths (e1:Expression,e2:Expression) : Type = mux_type_and_widths(tpe(e1),tpe(e2))
    def mux_type_and_widths (t1:Type,t2:Type) : Type = {
@@ -231,7 +231,7 @@ object Utils extends LazyLogging {
             case (t1:VectorType,t2:VectorType) => VectorType(mux_type_and_widths(t1.tpe,t2.tpe),t1.size)
             case (t1:BundleType,t2:BundleType) => BundleType((t1.fields zip t2.fields).map{case (f1, f2) => Field(f1.name,f1.flip,mux_type_and_widths(f1.tpe,f2.tpe))})
          }
-      } else UnknownType()
+      } else UnknownType
    }
    def module_type (m:DefModule) : Type = {
       BundleType(m.ports.map(p => p.toField))
@@ -239,7 +239,7 @@ object Utils extends LazyLogging {
    def sub_type (v:Type) : Type = {
       v match {
          case v:VectorType => v.tpe
-         case v => UnknownType()
+         case v => UnknownType
       }
    }
    def field_type (v:Type,s:String) : Type = {
@@ -248,33 +248,29 @@ object Utils extends LazyLogging {
             val ft = v.fields.find(p => p.name == s)
             ft match {
                case ft:Some[Field] => ft.get.tpe
-               case ft => UnknownType()
+               case ft => UnknownType
             }
          }
-         case v => UnknownType()
+         case v => UnknownType
       }
    }
    
 ////=====================================
    def widthBANG (t:Type) : Width = {
       t match {
-         case t:UIntType => t.width
-         case t:SIntType => t.width
-         case t:ClockType => IntWidth(1)
+         case g: GroundType => g.width
          case t => error("No width!")
       }
    }
    def long_BANG (t:Type) : Long = {
       (t) match {
-         case (t:UIntType) => t.width.as[IntWidth].get.width.toLong
-         case (t:SIntType) => t.width.as[IntWidth].get.width.toLong
+         case g: GroundType => g.width.as[IntWidth].get.width.toLong
          case (t:BundleType) => {
             var w = 0
             for (f <- t.fields) { w = w + long_BANG(f.tpe).toInt }
             w
          }
          case (t:VectorType) => t.size * long_BANG(t.tpe)
-         case (t:ClockType) => 1
       }
    }
 // =================================
@@ -288,7 +284,7 @@ object Utils extends LazyLogging {
          //case f: Field => f.getType
          case t: Type => t.getType
          case p: Port => p.getType
-         case _ => UnknownType()
+         case _ => UnknownType
        }
    }
 
@@ -409,10 +405,10 @@ object Utils extends LazyLogging {
             val ft = v.fields.find {p => p.name == s}
             ft match {
                case ft:Some[Field] => ft.get
-               case ft => error("Shouldn't be here"); Field("blah",DEFAULT,UnknownType())
+               case ft => error("Shouldn't be here"); Field("blah",DEFAULT,UnknownType)
             }
          }
-         case v => error("Shouldn't be here"); Field("blah",DEFAULT,UnknownType())
+         case v => error("Shouldn't be here"); Field("blah",DEFAULT,UnknownType)
       }
    }
    def times (flip:Flip,d:Direction) : Direction = times(flip, d)
@@ -518,8 +514,8 @@ object Utils extends LazyLogging {
          case e:ValidIf => e.tpe
          case e:UIntValue => UIntType(e.width)
          case e:SIntValue => SIntType(e.width)
-         case e:WVoid => UnknownType()
-         case e:WInvalid => UnknownType()
+         case e:WVoid => UnknownType
+         case e:WInvalid => UnknownType
       }
    def get_type (s:Stmt) : Type = {
       s match {
@@ -531,7 +527,7 @@ object Utils extends LazyLogging {
           val depth = s.depth
           val addr = Field("addr",DEFAULT,UIntType(IntWidth(scala.math.max(ceil_log2(depth), 1))))
           val en = Field("en",DEFAULT,BoolType())
-          val clk = Field("clk",DEFAULT,ClockType())
+          val clk = Field("clk",DEFAULT,ClockType)
           val def_data = Field("data",DEFAULT,s.data_type)
           val rev_data = Field("data",REVERSE,s.data_type)
           val mask = Field("mask",DEFAULT,create_mask(s.data_type))
@@ -547,9 +543,9 @@ object Utils extends LazyLogging {
           s.readwriters.foreach {x => mem_fields += Field(x,REVERSE,readwrite_type)}
           BundleType(mem_fields)
        }
-       case s:DefInstance => UnknownType()
+       case s:DefInstance => UnknownType
        case s:WDefInstance => s.tpe
-       case _ => UnknownType()
+       case _ => UnknownType
     }}
    def get_name (s:Stmt) : String = {
       s match {
@@ -725,7 +721,7 @@ object Utils extends LazyLogging {
          case s: DefWire    => s.tpe
          case s: DefRegister => s.tpe
          case s: DefMemory  => s.data_type
-         case _ => UnknownType()
+         case _ => UnknownType
        }
 
      def getInfo: Info =
@@ -772,7 +768,7 @@ object Utils extends LazyLogging {
 
    implicit class TypeUtils(t: Type) {
      def isGround: Boolean = t match {
-       case (_: UIntType | _: SIntType | _: ClockType) => true
+       case (_: UIntType | _: SIntType | ClockType) => true
        case (_: BundleType | _: VectorType) => false
      }
      def isAggregate: Boolean = !t.isGround
@@ -780,7 +776,7 @@ object Utils extends LazyLogging {
      def getType(): Type = 
        t match {
          case v: VectorType => v.tpe
-         case tpe: Type => UnknownType()
+         case tpe: Type => UnknownType
        }
 
      def wipeWidth(): Type = 
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index cee1d590..39e5c876 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -131,7 +131,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
                          else UIntType( UnknownWidth() )
           case "SInt" => if (ctx.getChildCount > 1) SIntType(IntWidth(string2BigInt(ctx.IntLit.getText))) 
                          else SIntType( UnknownWidth() )
-          case "Clock" => ClockType()
+          case "Clock" => ClockType
           case "{" => BundleType(ctx.field.map(visitField))
         }
       case tpe: TypeContext => new VectorType(visitType(ctx.`type`), string2Int(ctx.IntLit.getText))
@@ -236,7 +236,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
           case "<=" => Connect(info, visitExp(ctx.exp(0)), visitExp(ctx.exp(1)) )
           case "<-" => BulkConnect(info, visitExp(ctx.exp(0)), visitExp(ctx.exp(1)) )
           case "is" => IsInvalid(info, visitExp(ctx.exp(0)))
-          case "mport" => CDefMPort(info, ctx.id(0).getText, UnknownType(),ctx.id(1).getText,Seq(visitExp(ctx.exp(0)),visitExp(ctx.exp(1))),visitMdir(ctx.mdir))
+          case "mport" => CDefMPort(info, ctx.id(0).getText, UnknownType,ctx.id(1).getText,Seq(visitExp(ctx.exp(0)),visitExp(ctx.exp(1))),visitMdir(ctx.mdir))
         }
       }
     }
@@ -251,7 +251,7 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
   // - Add validif
 	private def visitExp[AST](ctx: FIRRTLParser.ExpContext): Expression = 
     if( ctx.getChildCount == 1 ) 
-      Ref((ctx.getText), UnknownType())
+      Ref((ctx.getText), UnknownType)
     else
       ctx.getChild(0).getText match {
         case "UInt" => { // This could be better
@@ -274,17 +274,17 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
             }
           SIntValue(value, width)
         }
-        case "validif(" => ValidIf(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), UnknownType())
-        case "mux(" => Mux(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), visitExp(ctx.exp(2)), UnknownType())
+        case "validif(" => ValidIf(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), UnknownType)
+        case "mux(" => Mux(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), visitExp(ctx.exp(2)), UnknownType)
         case _ => 
           ctx.getChild(1).getText match {
-            case "." => new SubField(visitExp(ctx.exp(0)), (ctx.id.getText), UnknownType())
+            case "." => new SubField(visitExp(ctx.exp(0)), (ctx.id.getText), UnknownType)
             case "[" => if (ctx.exp(1) == null)  
-                          new SubIndex(visitExp(ctx.exp(0)), string2Int(ctx.IntLit(0).getText), UnknownType())
-                        else new SubAccess(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), UnknownType())
+                          new SubIndex(visitExp(ctx.exp(0)), string2Int(ctx.IntLit(0).getText), UnknownType)
+                        else new SubAccess(visitExp(ctx.exp(0)), visitExp(ctx.exp(1)), UnknownType)
             // Assume primop
             case _ => DoPrim(visitPrimop(ctx.primop), ctx.exp.map(visitExp),
-                             ctx.IntLit.map(x => string2BigInt(x.getText)), UnknownType())
+                             ctx.IntLit.map(x => string2BigInt(x.getText)), UnknownType)
           }
       }
   
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index bb555112..d38efc35 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -53,10 +53,10 @@ case class WRef(name:String,tpe:Type,kind:Kind,gender:Gender) extends Expression
 case class WSubField(exp:Expression,name:String,tpe:Type,gender:Gender) extends Expression
 case class WSubIndex(exp:Expression,value:Int,tpe:Type,gender:Gender) extends Expression
 case class WSubAccess(exp:Expression,index:Expression,tpe:Type,gender:Gender) extends Expression
-case class WVoid() extends Expression { def tpe = UnknownType() }
-case class WInvalid() extends Expression { def tpe = UnknownType() }
+case class WVoid() extends Expression { def tpe = UnknownType }
+case class WInvalid() extends Expression { def tpe = UnknownType }
 // Useful for splitting then remerging references
-case object EmptyExpression extends Expression { def tpe = UnknownType() }
+case object EmptyExpression extends Expression { def tpe = UnknownType }
 case class WDefInstance(info:Info,name:String,module:String,tpe:Type) extends Stmt with IsDeclaration
 
 // Resultant width is the same as the maximum input width
@@ -125,7 +125,7 @@ class WrappedType (val t:Type) {
             (t,t2.t) match {
                case (t1:UIntType,t2:UIntType) => true
                case (t1:SIntType,t2:SIntType) => true
-               case (t1:ClockType,t2:ClockType) => true
+               case (ClockType, ClockType) => true
                case (t1:VectorType,t2:VectorType) => (wt(t1.tpe) == wt(t2.tpe) && t1.size == t2.size)
                case (t1:BundleType,t2:BundleType) => {
                   var ret = true
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index f9e91f67..88ba6ab2 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -423,7 +423,7 @@ object CheckTypes extends Pass with LazyLogging {
       def bulk_equals (t1: Type, t2: Type, flip1: Flip, flip2: Flip): Boolean = {
          //;println_all(["Inside with t1:" t1 ",t2:" t2 ",f1:" flip1 ",f2:" flip2])
          (t1,t2) match {
-            case (t1:ClockType,t2:ClockType) => flip1 == flip2
+            case (ClockType, ClockType) => flip1 == flip2
             case (t1:UIntType,t2:UIntType) => flip1 == flip2
             case (t1:SIntType,t2:SIntType) => flip1 == flip2
             case (t1:BundleType,t2:BundleType) => {
@@ -450,14 +450,14 @@ object CheckTypes extends Pass with LazyLogging {
             case (s:DefRegister) => if (wt(s.tpe) != wt(tpe(s.init))) errors.append(new InvalidRegInit(s.info))
             case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp),DEFAULT,DEFAULT) ) errors.append(new InvalidConnect(s.info, s.loc.serialize, s.exp.serialize))
             case (s:Stop) => {
-               if (wt(tpe(s.clk)) != wt(ClockType()) ) errors.append(new ReqClk(s.info))
+               if (wt(tpe(s.clk)) != wt(ClockType) ) errors.append(new ReqClk(s.info))
                if (wt(tpe(s.en)) != wt(ut()) ) errors.append(new EnNotUInt(s.info))
             }
             case (s:Print)=> {
                for (x <- s.args ) {
                   if (wt(tpe(x)) != wt(ut()) && wt(tpe(x)) != wt(st()) ) errors.append(new PrintfArgNotGround(s.info))
                }
-               if (wt(tpe(s.clk)) != wt(ClockType()) ) errors.append(new ReqClk(s.info))
+               if (wt(tpe(s.clk)) != wt(ClockType) ) errors.append(new ReqClk(s.info))
                if (wt(tpe(s.en)) != wt(ut()) ) errors.append(new EnNotUInt(s.info))
             }
             case (s:Conditionally) => if (wt(tpe(s.pred)) != wt(ut()) ) errors.append(new PredNotUInt(s.info))
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index 38f67426..05d46e42 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -110,7 +110,7 @@ object LowerTypes extends Pass {
             val exps = create_exps(mem.name, memType)
             exps map { e =>
               val loMemName = loweredName(e)
-              val loMem = WRef(loMemName, UnknownType(), kind(mem), UNKNOWNGENDER)
+              val loMem = WRef(loMemName, UnknownType, kind(mem), UNKNOWNGENDER)
               mergeRef(loMem, mergeRef(port, field))
             }
           }
@@ -122,7 +122,7 @@ object LowerTypes extends Pass {
             case Some(e) =>
               val loMemExp = mergeRef(mem, e)
               val loMemName = loweredName(loMemExp)
-              WRef(loMemName, UnknownType(), kind(mem), UNKNOWNGENDER)
+              WRef(loMemName, UnknownType, kind(mem), UNKNOWNGENDER)
             case None => mem
           }
           Seq(mergeRef(loMem, mergeRef(port, field)))
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index dd2a139b..f9a79f54 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -78,7 +78,7 @@ object ToWorkingIR extends Pass {
       }
       def toStmt (s:Stmt) : Stmt = {
          s map (toExp) match {
-            case s:DefInstance => WDefInstance(s.info,s.name,s.module,UnknownType())
+            case s:DefInstance => WDefInstance(s.info,s.name,s.module,UnknownType)
             case s => s map (toStmt)
          }
       }
@@ -479,7 +479,7 @@ object InferWidths extends Pass {
       (t) match {
          case (t:UIntType) => t.width
          case (t:SIntType) => t.width
-         case (t:ClockType) => IntWidth(1)
+         case ClockType => IntWidth(1)
          case (t) => error("No width!"); IntWidth(-1) } }
    def width_BANG (e:Expression) : Width = width_BANG(tpe(e))
 
@@ -1047,15 +1047,15 @@ object CInferTypes extends Pass {
          case (v:BundleType) => {
             val ft = v.fields.find(p => p.name == s)
             if (ft != None) ft.get.tpe
-            else  UnknownType()
+            else  UnknownType
          }
-         case (v) => UnknownType()
+         case (v) => UnknownType
       }
    }
    def sub_type (v:Type) : Type =
       (v) match { 
          case (v:VectorType) => v.tpe
-         case (v) => UnknownType()
+         case (v) => UnknownType
       }
    def run (c:Circuit) : Circuit = {
       val module_types = LinkedHashMap[String,Type]()
@@ -1063,7 +1063,7 @@ object CInferTypes extends Pass {
          val types = LinkedHashMap[String,Type]()
          def infer_types_e (e:Expression) : Expression = {
             (e map (infer_types_e)) match { 
-               case (e:Ref) => Ref(e.name, types.getOrElse(e.name,UnknownType()))
+               case (e:Ref) => Ref(e.name, types.getOrElse(e.name,UnknownType))
                case (e:SubField) => SubField(e.exp,e.name,field_type(tpe(e.exp),e.name))
                case (e:SubIndex) => SubIndex(e.exp,e.value,sub_type(tpe(e.exp)))
                case (e:SubAccess) => SubAccess(e.exp,e.index,sub_type(tpe(e.exp)))
@@ -1099,7 +1099,7 @@ object CInferTypes extends Pass {
                   s
                }
                case (s:CDefMPort) => {
-                  val t = types.getOrElse(s.mem,UnknownType())
+                  val t = types.getOrElse(s.mem,UnknownType)
                   types(s.name) = t
                   CDefMPort(s.info,s.name,t,s.mem,s.exps,s.direction)
                }
@@ -1108,7 +1108,7 @@ object CInferTypes extends Pass {
                   s
                }
                case (s:DefInstance) => {
-                  types(s.name) = module_types.getOrElse(s.module,UnknownType())
+                  types(s.name) = module_types.getOrElse(s.module,UnknownType)
                   s
                }
                case (s) => s map(infer_types_s) map (infer_types_e)
@@ -1227,12 +1227,12 @@ object RemoveCHIRRTL extends Pass {
                ValidIf(e.cond,e1,tpe(e1))
             })
          case (e) => (tpe(e)) match  { 
-            case (_:UIntType|_:SIntType|_:ClockType) => Seq(e)
+            case (_:UIntType|_:SIntType|ClockType) => Seq(e)
             case (t:BundleType) => 
                t.fields.flatMap(f => create_exps(SubField(e,f.name,f.tpe)))
             case (t:VectorType)=> 
                (0 until t.size).flatMap(i => create_exps(SubIndex(e,i,t.tpe)))
-            case (t:UnknownType) => Seq(e)
+            case UnknownType => Seq(e)
          }
       }
    }
@@ -1240,7 +1240,7 @@ object RemoveCHIRRTL extends Pass {
       def remove_chirrtl_m (m:Module) : Module = {
          val hash = LinkedHashMap[String,MPorts]()
          val repl = LinkedHashMap[String,DataRef]()
-         val ut = UnknownType()
+         val ut = UnknownType
          val mport_types = LinkedHashMap[String,Type]()
          def EMPs () : MPorts = MPorts(ArrayBuffer[MPort](),ArrayBuffer[MPort](),ArrayBuffer[MPort]())
          def collect_mports (s:Stmt) : Stmt = {