API Cleanup - Port & Direction

Add simple documentation
Change Direction case objects to upper camel case

7 files changed, 28 insertions, 26 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 85588a53..2b19f24e 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -108,8 +108,8 @@ class VerilogEmitter extends Emitter {
          }
          case (p:Direction) => {
             p match {
-               case INPUT => w.get.write("input")
-               case OUTPUT => w.get.write("output")
+               case Input => w.get.write("input")
+               case Output => w.get.write("output")
             }
          }
          case (s:String) => w.get.write(s)
@@ -438,8 +438,8 @@ class VerilogEmitter extends Emitter {
       def build_ports () = {
          (m.ports,0 until m.ports.size).zipped.foreach{(p,i) => {
             p.direction match {
-               case INPUT => portdefs += Seq(p.direction,"  ",p.tpe," ",p.name)
-               case OUTPUT => {
+               case Input => portdefs += Seq(p.direction,"  ",p.tpe," ",p.name)
+               case Output => {
                   portdefs += Seq(p.direction," ",p.tpe," ",p.name)
                   val ex = WRef(p.name,p.tpe,PortKind(),FEMALE)
                   assign(ex,netlist(ex))
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index 7721a563..d9dab2d9 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -161,10 +161,12 @@ case class VectorType(tpe: Type, size: Int) extends Type
 case class ClockType() extends Type
 case class UnknownType() extends Type
 
-trait Direction extends AST
-case object INPUT extends Direction
-case object OUTPUT extends Direction
+/** [[Port]] Direction */
+abstract class Direction extends AST
+case object Input extends Direction
+case object Output extends Direction
 
+/** [[DefModule]] Port */
 case class Port(info: Info, name: String, direction: Direction, tpe: Type) extends AST with IsDeclaration
 
 /** Base class for modules */
diff --git a/src/main/scala/firrtl/Serialize.scala b/src/main/scala/firrtl/Serialize.scala
index ad0efa66..5a5b690d 100644
--- a/src/main/scala/firrtl/Serialize.scala
+++ b/src/main/scala/firrtl/Serialize.scala
@@ -193,8 +193,8 @@ class Serialize {
 
   def serialize(d: Direction): String = {
     d match {
-      case INPUT => "input"
-      case OUTPUT => "output"
+      case Input => "input"
+      case Output => "output"
     }
   }
 
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 658b0d9a..9c0a59cb 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -360,8 +360,8 @@ object Utils extends LazyLogging {
    }
    def swap (d:Direction) : Direction = {
       d match {
-         case OUTPUT => INPUT
-         case INPUT => OUTPUT
+         case Output => Input
+         case Input => Output
       }
    }
    def swap (f:Flip) : Flip = {
@@ -372,14 +372,14 @@ object Utils extends LazyLogging {
    }
    def to_dir (g:Gender) : Direction = {
       g match {
-         case MALE => INPUT
-         case FEMALE => OUTPUT
+         case MALE => Input
+         case FEMALE => Output
       }
    }
    def to_gender (d:Direction) : Gender = {
       d match {
-         case INPUT => MALE
-         case OUTPUT => FEMALE
+         case Input => MALE
+         case Output => FEMALE
       }
    }
   def toGender(f: Flip): Gender = f match {
@@ -495,7 +495,7 @@ object Utils extends LazyLogging {
        case s:IsInvalid => UNKNOWNGENDER
      }
    def get_gender (p:Port) : Gender =
-     if (p.direction == INPUT) MALE else FEMALE
+     if (p.direction == Input) MALE else FEMALE
    def kind (e:Expression) : Kind =
       e match {
          case e:WRef => e.kind
@@ -756,8 +756,8 @@ object Utils extends LazyLogging {
          
      def toDirection(): Direction = {
        f match {
-         case DEFAULT => OUTPUT
-         case REVERSE => INPUT
+         case DEFAULT => Output
+         case REVERSE => Input
        }
      }
    }
@@ -794,8 +794,8 @@ object Utils extends LazyLogging {
    implicit class DirectionUtils(d: Direction) {
      def toFlip(): Flip = {
        d match {
-         case INPUT => REVERSE
-         case OUTPUT => DEFAULT
+         case Input => REVERSE
+         case Output => DEFAULT
        }
      }
    }
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index cc6f900c..cee1d590 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -111,8 +111,8 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
   }
   private def visitDir[AST](ctx: FIRRTLParser.DirContext): Direction =
     ctx.getText match {
-      case "input" => INPUT
-      case "output" => OUTPUT
+      case "input" => Input
+      case "output" => Output
     }
   private def visitMdir[AST](ctx: FIRRTLParser.MdirContext): MPortDir =
     ctx.getText match {
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index fb19ca8d..f9e91f67 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -486,8 +486,8 @@ object CheckGenders extends Pass {
    
    def dir_to_gender (d:Direction) : Gender = {
       d match {
-         case INPUT => MALE
-         case OUTPUT => FEMALE //BI-GENDER
+         case Input => MALE
+         case Output => FEMALE //BI-GENDER
       }
    }
    
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index d1c0a647..dd2a139b 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -1037,8 +1037,8 @@ object CInferTypes extends Pass {
    }
    
    def to_field (p:Port) : Field = {
-      if (p.direction == OUTPUT) Field(p.name,DEFAULT,p.tpe)
-      else if (p.direction == INPUT) Field(p.name,REVERSE,p.tpe)
+      if (p.direction == Output) Field(p.name,DEFAULT,p.tpe)
+      else if (p.direction == Input) Field(p.name,REVERSE,p.tpe)
       else error("Shouldn't be here"); Field(p.name,REVERSE,p.tpe)
    }
    def module_type (m:DefModule) : Type = BundleType(m.ports.map(p => to_field(p)))