API Cleanup - Module

trait Module -> abstract class DefModule
InModule -> Module (match concrete syntax)
ExModule -> ExtModule (match concrete syntax)
Add simple scaladoc for each one

20 files changed, 142 insertions, 133 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index f871c82a..85588a53 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -272,7 +272,7 @@ class VerilogEmitter extends Emitter {
       }
    }
    
-   def emit_verilog (m:InModule) : Module = {
+   def emit_verilog (m:Module) : DefModule = {
       mname = m.name
       val netlist = LinkedHashMap[WrappedExpression,Expression]()
       val simlist = ArrayBuffer[Stmt]()
@@ -655,8 +655,8 @@ class VerilogEmitter extends Emitter {
       this.w = Some(w)
       for (m <- c.modules) {
          m match {
-            case (m:InModule) => emit_verilog(m)
-            case (m:ExModule) => false
+            case (m:Module) => emit_verilog(m)
+            case (m:ExtModule) => false
          }
       }
    }
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index c762b198..7721a563 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -167,13 +167,22 @@ case object OUTPUT extends Direction
 
 case class Port(info: Info, name: String, direction: Direction, tpe: Type) extends AST with IsDeclaration
 
-trait Module extends AST with IsDeclaration {
+/** Base class for modules */
+abstract class DefModule extends AST with IsDeclaration {
   val info : Info
   val name : String
   val ports : Seq[Port]
 }
-case class InModule(info: Info, name: String, ports: Seq[Port], body: Stmt) extends Module
-case class ExModule(info: Info, name: String, ports: Seq[Port]) extends Module
-
-case class Circuit(info: Info, modules: Seq[Module], main: String) extends AST with HasInfo
+/** Internal Module
+  *
+  * An instantiable hardware block
+  */
+case class Module(info: Info, name: String, ports: Seq[Port], body: Stmt) extends DefModule
+/** External Module
+  *
+  * Generally used for Verilog black boxes
+  */
+case class ExtModule(info: Info, name: String, ports: Seq[Port]) extends DefModule
+
+case class Circuit(info: Info, modules: Seq[DefModule], main: String) extends AST with HasInfo
 
diff --git a/src/main/scala/firrtl/Mappers.scala b/src/main/scala/firrtl/Mappers.scala
index 335bc4aa..0ee8165b 100644
--- a/src/main/scala/firrtl/Mappers.scala
+++ b/src/main/scala/firrtl/Mappers.scala
@@ -196,36 +196,36 @@ object Mappers {
 
   // ********** Module Mappers **********
   private trait ModuleMagnet {
-    def map(module: Module): Module
+    def map(module: DefModule): DefModule
   }
   private object ModuleMagnet {
     implicit def forStmt(f: Stmt => Stmt) = new ModuleMagnet {
-      override def map(module: Module): Module = {
+      override def map(module: DefModule): DefModule = {
         module match {
-          case m: InModule => InModule(m.info, m.name, m.ports, f(m.body))
-          case m: ExModule => m
+          case m: Module => Module(m.info, m.name, m.ports, f(m.body))
+          case m: ExtModule => m
         }
       }
     }
     implicit def forPorts(f: Port => Port) = new ModuleMagnet {
-      override def map(module: Module): Module = {
+      override def map(module: DefModule): DefModule = {
         module match {
-          case m: InModule => InModule(m.info, m.name, m.ports.map(f), m.body)
-          case m: ExModule => ExModule(m.info, m.name, m.ports.map(f))
+          case m: Module => Module(m.info, m.name, m.ports.map(f), m.body)
+          case m: ExtModule => ExtModule(m.info, m.name, m.ports.map(f))
         }
       }
     }
     implicit def forString(f: String => String) = new ModuleMagnet {
-      override def map(module: Module): Module = {
+      override def map(module: DefModule): DefModule = {
         module match {
-          case m: InModule => InModule(m.info, f(m.name), m.ports, m.body)
-          case m: ExModule => ExModule(m.info, f(m.name), m.ports)
+          case m: Module => Module(m.info, f(m.name), m.ports, m.body)
+          case m: ExtModule => ExtModule(m.info, f(m.name), m.ports)
         }
       }
     }
   }
-  implicit class ModuleMap(module: Module) {
-    def map[T](f: T => T)(implicit magnet: (T => T) => ModuleMagnet): Module = magnet(f).map(module)
+  implicit class ModuleMap(module: DefModule) {
+    def map[T](f: T => T)(implicit magnet: (T => T) => ModuleMagnet): DefModule = magnet(f).map(module)
   }
 
 }
diff --git a/src/main/scala/firrtl/Namespace.scala b/src/main/scala/firrtl/Namespace.scala
index 01cc59fd..8e89cbf2 100644
--- a/src/main/scala/firrtl/Namespace.scala
+++ b/src/main/scala/firrtl/Namespace.scala
@@ -59,7 +59,7 @@ object Namespace {
   def apply(): Namespace = new Namespace
 
   // Initializes a namespace from a Module
-  def apply(m: Module): Namespace = {
+  def apply(m: DefModule): Namespace = {
     val namespace = new Namespace
 
     def buildNamespaceStmt(s: Stmt): Stmt =
@@ -77,7 +77,7 @@ object Namespace {
     }
     m.ports map buildNamespacePort
     m match {
-      case in: InModule => buildNamespaceStmt(in.body)
+      case in: Module => buildNamespaceStmt(in.body)
       case _ => // Do nothing
     }
 
diff --git a/src/main/scala/firrtl/Serialize.scala b/src/main/scala/firrtl/Serialize.scala
index 1735c270..ad0efa66 100644
--- a/src/main/scala/firrtl/Serialize.scala
+++ b/src/main/scala/firrtl/Serialize.scala
@@ -43,7 +43,7 @@ private object Serialize {
       case r: Type => ser.serialize(r)
       case r: Direction => ser.serialize(r)
       case r: Port => ser.serialize(r)
-      case r: Module => ser.serialize(r)
+      case r: DefModule => ser.serialize(r)
       case r: Circuit => ser.serialize(r)
       case r: StringLit => ser.serialize(r)
       case _ => throw new Exception("serialize called on unknown AST node!")
@@ -201,9 +201,9 @@ class Serialize {
   def serialize(p: Port): String =
     s"${serialize(p.direction)} ${p.name} : ${serialize(p.tpe)}${p.info}"
 
-  def serialize(m: Module): String = {
+  def serialize(m: DefModule): String = {
     m match {
-      case m: InModule => {
+      case m: Module => {
         var s = new StringBuilder(s"module ${m.name} :${m.info}")
         withIndent {
           s ++= m.ports.map(newline ++ serialize(_)).mkString
@@ -211,7 +211,7 @@ class Serialize {
         }
         s.toString
       }
-      case m: ExModule => {
+      case m: ExtModule => {
         var s = new StringBuilder(s"extmodule ${m.name} :${m.info}")
         withIndent {
           s ++= m.ports.map(newline ++ serialize(_)).mkString
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index a2ca3103..658b0d9a 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -233,7 +233,7 @@ object Utils extends LazyLogging {
          }
       } else UnknownType()
    }
-   def module_type (m:Module) : Type = {
+   def module_type (m:DefModule) : Type = {
       BundleType(m.ports.map(p => p.toField))
    }
    def sub_type (v:Type) : Type = {
@@ -620,12 +620,12 @@ object Utils extends LazyLogging {
 
   /** Gets the root declaration of an expression
     *
-    * @param m the [[firrtl.InModule]] to search
+    * @param m    the [[firrtl.Module]] to search
     * @param expr the [[firrtl.Expression]] that refers to some declaration
     * @return the [[firrtl.IsDeclaration]] of `expr`
     * @throws DeclarationNotFoundException if no declaration of `expr` is found
     */
-  def getDeclaration(m: InModule, expr: Expression): IsDeclaration = {
+  def getDeclaration(m: Module, expr: Expression): IsDeclaration = {
     def getRootDecl(name: String)(s: Stmt): Option[IsDeclaration] = s match {
       case decl: IsDeclaration => if (decl.name == name) Some(decl) else None
       case c: Conditionally =>
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index f2a3953b..cc6f900c 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -98,11 +98,11 @@ class Visitor(infoMode: InfoMode) extends FIRRTLBaseVisitor[AST]
 	private def visitCircuit[AST](ctx: FIRRTLParser.CircuitContext): Circuit =
     Circuit(visitInfo(Option(ctx.info), ctx), ctx.module.map(visitModule), (ctx.id.getText))
     
-  private def visitModule[AST](ctx: FIRRTLParser.ModuleContext): Module = {
+  private def visitModule[AST](ctx: FIRRTLParser.ModuleContext): DefModule = {
     val info = visitInfo(Option(ctx.info), ctx)
     ctx.getChild(0).getText match {
-      case "module" => InModule(info, ctx.id.getText, ctx.port.map(visitPort), visitBlock(ctx.block))
-      case "extmodule" => ExModule(info, ctx.id.getText, ctx.port.map(visitPort))
+      case "module" => Module(info, ctx.id.getText, ctx.port.map(visitPort), visitBlock(ctx.block))
+      case "extmodule" => ExtModule(info, ctx.id.getText, ctx.port.map(visitPort))
     }
   }
 
diff --git a/src/main/scala/firrtl/passes/CheckInitialization.scala b/src/main/scala/firrtl/passes/CheckInitialization.scala
index 27857768..493b7a3a 100644
--- a/src/main/scala/firrtl/passes/CheckInitialization.scala
+++ b/src/main/scala/firrtl/passes/CheckInitialization.scala
@@ -62,7 +62,7 @@ object CheckInitialization extends Pass {
     val errors = collection.mutable.ArrayBuffer[PassException]()
 
 
-    def checkInitM(m: InModule): Unit = {
+    def checkInitM(m: Module): Unit = {
       val voidExprs = collection.mutable.HashMap[WrappedExpression, VoidExpr]()
 
       def hasVoidExpr(e: Expression): (Boolean, Seq[Expression]) = {
@@ -116,7 +116,7 @@ object CheckInitialization extends Pass {
 
     c.modules foreach { m =>
       m match {
-        case m: InModule => checkInitM(m)
+        case m: Module => checkInitM(m)
         case m => // Do nothing
       }
     }
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 23613e65..fb19ca8d 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -169,7 +169,7 @@ object CheckHighForm extends Pass with LazyLogging {
       t map (checkHighFormW)
     }
 
-    def checkHighFormM(m: Module): Module = {
+    def checkHighFormM(m: DefModule): DefModule = {
       val names = HashMap[String, Boolean]()
       val mnames = HashMap[String, Boolean]()
       def checkHighFormE(e: Expression): Expression = {
@@ -243,8 +243,8 @@ object CheckHighForm extends Pass with LazyLogging {
       }
 
       m match {
-        case m: InModule => checkHighFormS(m.body)
-        case m: ExModule => // Do Nothing
+        case m: Module => checkHighFormS(m.body)
+        case m: ExtModule => // Do Nothing
       }
       m
     }
@@ -470,8 +470,8 @@ object CheckTypes extends Pass with LazyLogging {
       for (m <- c.modules ) {
          mname = m.name
          (m) match { 
-            case (m:ExModule) => false
-            case (m:InModule) => check_types_s(m.body)
+            case (m:ExtModule) => false
+            case (m:Module) => check_types_s(m.body)
          }
       }
       errors.trigger
@@ -635,8 +635,8 @@ object CheckGenders extends Pass {
             genders(p.name) = dir_to_gender(p.direction)
          }
          (m) match { 
-            case (m:ExModule) => false
-            case (m:InModule) => check_genders_s(genders)(m.body)
+            case (m:ExtModule) => false
+            case (m:Module) => check_genders_s(genders)(m.body)
          }
       }
       errors.trigger
@@ -654,7 +654,7 @@ object CheckWidths extends Pass {
    class NegWidthException(info:Info) extends PassException(s"${info}: [module ${mname}] Width cannot be negative or zero.")
    def run (c:Circuit): Circuit = {
       val errors = new Errors()
-      def check_width_m (m:Module) : Unit = {
+      def check_width_m (m:DefModule) : Unit = {
          def check_width_w (info:Info)(w:Width) : Width = {
             (w) match { 
                case (w:IntWidth)=> if (w.width <= 0) errors.append(new NegWidthException(info))
@@ -698,8 +698,8 @@ object CheckWidths extends Pass {
          }
    
          (m) match { 
-            case (m:ExModule) => {}
-            case (m:InModule) => check_width_s(m.body)
+            case (m:ExtModule) => {}
+            case (m:Module) => check_width_s(m.body)
          }
       }
       
diff --git a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
index 717d95e8..35bd86ce 100644
--- a/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
+++ b/src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala
@@ -76,8 +76,8 @@ object CommonSubexpressionElimination extends Pass {
 
   def run(c: Circuit): Circuit = {
     val modulesx = c.modules.map {
-      case m: ExModule => m
-      case m: InModule => InModule(m.info, m.name, m.ports, cse(m.body))
+      case m: ExtModule => m
+      case m: Module => Module(m.info, m.name, m.ports, cse(m.body))
     }
     Circuit(c.info, modulesx, c.main)
   }
diff --git a/src/main/scala/firrtl/passes/ConstProp.scala b/src/main/scala/firrtl/passes/ConstProp.scala
index 216e94b0..7c78e283 100644
--- a/src/main/scala/firrtl/passes/ConstProp.scala
+++ b/src/main/scala/firrtl/passes/ConstProp.scala
@@ -256,7 +256,7 @@ object ConstProp extends Pass {
   }
 
   @tailrec
-  private def constPropModule(m: InModule): InModule = {
+  private def constPropModule(m: Module): Module = {
     var nPropagated = 0L
     val nodeMap = collection.mutable.HashMap[String, Expression]()
 
@@ -281,14 +281,14 @@ object ConstProp extends Pass {
       s map constPropStmt map constPropExpression
     }
 
-    val res = InModule(m.info, m.name, m.ports, constPropStmt(m.body))
+    val res = Module(m.info, m.name, m.ports, constPropStmt(m.body))
     if (nPropagated > 0) constPropModule(res) else res
   }
 
   def run(c: Circuit): Circuit = {
     val modulesx = c.modules.map {
-      case m: ExModule => m
-      case m: InModule => constPropModule(m)
+      case m: ExtModule => m
+      case m: Module => constPropModule(m)
     }
     Circuit(c.info, modulesx, c.main)
   }
diff --git a/src/main/scala/firrtl/passes/DeadCodeElimination.scala b/src/main/scala/firrtl/passes/DeadCodeElimination.scala
index cb772556..cdff1639 100644
--- a/src/main/scala/firrtl/passes/DeadCodeElimination.scala
+++ b/src/main/scala/firrtl/passes/DeadCodeElimination.scala
@@ -76,8 +76,8 @@ object DeadCodeElimination extends Pass {
 
   def run(c: Circuit): Circuit = {
     val modulesx = c.modules.map {
-      case m: ExModule => m
-      case m: InModule => InModule(m.info, m.name, m.ports, dce(m.body))
+      case m: ExtModule => m
+      case m: Module => Module(m.info, m.name, m.ports, dce(m.body))
     }
     Circuit(c.info, modulesx, c.main)
   }
diff --git a/src/main/scala/firrtl/passes/ExpandWhens.scala b/src/main/scala/firrtl/passes/ExpandWhens.scala
index 540aab9f..d68b1eaa 100644
--- a/src/main/scala/firrtl/passes/ExpandWhens.scala
+++ b/src/main/scala/firrtl/passes/ExpandWhens.scala
@@ -102,7 +102,7 @@ object ExpandWhens extends Pass {
 
   // ------------ Pass -------------------
   def run(c: Circuit): Circuit = {
-    def expandWhens(m: InModule): (LinkedHashMap[WrappedExpression, Expression], ArrayBuffer[Stmt], Stmt) = {
+    def expandWhens(m: Module): (LinkedHashMap[WrappedExpression, Expression], ArrayBuffer[Stmt], Stmt) = {
       val namespace = Namespace(m)
       val simlist = ArrayBuffer[Stmt]()
 
@@ -187,11 +187,11 @@ object ExpandWhens extends Pass {
     }
     val modulesx = c.modules map { m =>
       m match {
-        case m: ExModule => m
-        case m: InModule =>
+        case m: ExtModule => m
+        case m: Module =>
         val (netlist, simlist, bodyx) = expandWhens(m)
         val newBody = Begin(Seq(bodyx map squashEmpty) ++ expandNetlist(netlist) ++ simlist)
-        InModule(m.info, m.name, m.ports, newBody)
+        Module(m.info, m.name, m.ports, newBody)
       }
     }
     Circuit(c.info, modulesx, c.main)
diff --git a/src/main/scala/firrtl/passes/Inline.scala b/src/main/scala/firrtl/passes/Inline.scala
index 5e523a37..f1b71149 100644
--- a/src/main/scala/firrtl/passes/Inline.scala
+++ b/src/main/scala/firrtl/passes/Inline.scala
@@ -47,7 +47,7 @@ object InlineInstances extends Transform {
          if (!moduleMap.contains(name))
             errors += new PassException(s"Annotated module does not exist: ${name}")
       def checkExternal(name: String): Unit = moduleMap(name) match {
-            case m: ExModule => errors += new PassException(s"Annotated module cannot be an external module: ${name}")
+            case m: ExtModule => errors += new PassException(s"Annotated module cannot be an external module: ${name}")
             case _ => {}
          }
       def checkInstance(cn: ComponentName): Unit = {
@@ -63,7 +63,7 @@ object InlineInstances extends Transform {
             }
             s map onStmt(name)
          }
-         onStmt(cn.name)(moduleMap(cn.module.name).asInstanceOf[InModule].body)
+         onStmt(cn.name)(moduleMap(cn.module.name).asInstanceOf[Module].body)
          if (!containsCN) errors += new PassException(s"Annotated instance does not exist: ${cn.module.name}.${cn.name}")
       }
       annModuleNames.foreach{n => checkExists(n)}
@@ -85,12 +85,12 @@ object InlineInstances extends Transform {
 
       // ---- Pass functions/data ----
       // Contains all unaltered modules
-      val originalModules = mutable.HashMap[String,Module]()
+      val originalModules = mutable.HashMap[String,DefModule]()
       // Contains modules whose direct/indirect children modules have been inlined, and whose tagged instances have been inlined.
-      val inlinedModules = mutable.HashMap[String,Module]()
+      val inlinedModules = mutable.HashMap[String,DefModule]()
 
       // Recursive.
-      def onModule(m: Module): Module = {
+      def onModule(m: DefModule): DefModule = {
          val inlinedInstances = mutable.ArrayBuffer[String]()
          // Recursive. Replaces inst.port with inst$port
          def onExp(e: Expression): Expression = e match {
@@ -136,8 +136,8 @@ object InlineInstances extends Transform {
                   if (shouldInline) {
                      inlinedInstances += instName
                      val instInModule = instModule match {
-                        case m: ExModule => throw new PassException("Cannot inline external module")
-                        case m: InModule => m
+                        case m: ExtModule => throw new PassException("Cannot inline external module")
+                        case m: Module => m
                      }
                      val stmts = mutable.ArrayBuffer[Stmt]()
                      for (p <- instInModule.ports) {
@@ -150,12 +150,12 @@ object InlineInstances extends Transform {
                case s => s map onExp map onStmt
             }
          m match {
-            case InModule(info, name, ports, body) => {
-               val mx = InModule(info, name, ports, onStmt(body))
+            case Module(info, name, ports, body) => {
+               val mx = Module(info, name, ports, onStmt(body))
                inlinedModules(name) = mx
                mx
             }
-            case m: ExModule => {
+            case m: ExtModule => {
                inlinedModules(m.name) = m
                m
             }
diff --git a/src/main/scala/firrtl/passes/LowerTypes.scala b/src/main/scala/firrtl/passes/LowerTypes.scala
index 1dc3f782..38f67426 100644
--- a/src/main/scala/firrtl/passes/LowerTypes.scala
+++ b/src/main/scala/firrtl/passes/LowerTypes.scala
@@ -88,7 +88,7 @@ object LowerTypes extends Pass {
     implicit var mname: String = ""
     implicit var sinfo: Info = NoInfo
 
-    def lowerTypes(m: Module): Module = {
+    def lowerTypes(m: DefModule): DefModule = {
       val memDataTypeMap = HashMap[String, Type]()
 
       // Lowers an expression of MemKind
@@ -251,8 +251,8 @@ object LowerTypes extends Pass {
         exps map ( e => Port(p.info, loweredName(e), to_dir(gender(e)), tpe(e)) )
       }
       m match {
-        case m: ExModule => m.copy(ports = portsx)
-        case m: InModule => InModule(m.info, m.name, portsx, lowerTypesStmt(m.body))
+        case m: ExtModule => m.copy(ports = portsx)
+        case m: Module => Module(m.info, m.name, portsx, lowerTypesStmt(m.body))
       }
     }
 
diff --git a/src/main/scala/firrtl/passes/PadWidths.scala b/src/main/scala/firrtl/passes/PadWidths.scala
index 049da53b..58725928 100644
--- a/src/main/scala/firrtl/passes/PadWidths.scala
+++ b/src/main/scala/firrtl/passes/PadWidths.scala
@@ -70,10 +70,10 @@ object PadWidths extends Pass {
          case s => s map onStmt
       }
    }
-   private def onModule(m: Module): Module = {
+   private def onModule(m: DefModule): DefModule = {
       m match {
-         case m:InModule => InModule(m.info, m.name, m.ports, onStmt(m.body))
-         case m:ExModule => m
+         case m: Module => Module(m.info, m.name, m.ports, onStmt(m.body))
+         case m: ExtModule => m
       }
    }
    def run(c: Circuit): Circuit = Circuit(c.info, c.modules.map(onModule _), c.main)
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index abd758bf..d1c0a647 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -85,8 +85,8 @@ object ToWorkingIR extends Pass {
       val modulesx = c.modules.map { m => 
          mname = m.name
          m match {
-            case m:InModule => InModule(m.info,m.name, m.ports, toStmt(m.body))
-            case m:ExModule => m
+            case m:Module => Module(m.info,m.name, m.ports, toStmt(m.body))
+            case m:ExtModule => m
          }
       }
       Circuit(c.info,modulesx,c.main)
@@ -97,7 +97,7 @@ object ResolveKinds extends Pass {
    private var mname = ""
    def name = "Resolve Kinds"
    def run (c:Circuit): Circuit = {
-      def resolve_kinds (m:Module, c:Circuit):Module = {
+      def resolve_kinds (m:DefModule, c:Circuit):DefModule = {
          val kinds = LinkedHashMap[String,Kind]()
          def resolve (body:Stmt) = {
             def resolve_expr (e:Expression):Expression = {
@@ -110,7 +110,7 @@ object ResolveKinds extends Pass {
             resolve_stmt(body)
          }
    
-         def find (m:Module) = {
+         def find (m:DefModule) = {
             def find_stmt (s:Stmt):Stmt = {
                s match {
                   case s:DefWire => kinds(s.name) = WireKind()
@@ -125,19 +125,19 @@ object ResolveKinds extends Pass {
             }
             m.ports.foreach { p => kinds(p.name) = PortKind() }
             m match {
-               case m:InModule => find_stmt(m.body)
-               case m:ExModule => false
+               case m:Module => find_stmt(m.body)
+               case m:ExtModule => false
             }
          }
        
          mname = m.name
          find(m)   
          m match {
-            case m:InModule => {
+            case m:Module => {
                val bodyx = resolve(m.body)
-               InModule(m.info,m.name,m.ports,bodyx)
+               Module(m.info,m.name,m.ports,bodyx)
             }
-            case m:ExModule => ExModule(m.info,m.name,m.ports)
+            case m:ExtModule => ExtModule(m.info,m.name,m.ports)
          }
       }
       val modulesx = c.modules.map(m => resolve_kinds(m,c))
@@ -167,7 +167,7 @@ object InferTypes extends Pass {
    def run (c:Circuit): Circuit = {
       val module_types = LinkedHashMap[String,Type]()
       implicit val wnamespace = Namespace()
-      def infer_types (m:Module) : Module = {
+      def infer_types (m:DefModule) : DefModule = {
          val types = LinkedHashMap[String,Type]()
          def infer_types_e (e:Expression) : Expression = {
             e map (infer_types_e) match {
@@ -224,8 +224,8 @@ object InferTypes extends Pass {
          mname = m.name
          m.ports.foreach(p => types(p.name) = p.tpe)
          m match {
-            case m:InModule => InModule(m.info,m.name,m.ports,infer_types_s(m.body))
-            case m:ExModule => m
+            case m:Module => Module(m.info,m.name,m.ports,infer_types_s(m.body))
+            case m:ExtModule => m
          }
        }
  
@@ -234,8 +234,8 @@ object InferTypes extends Pass {
             mname = m.name
             val portsx = m.ports.map(p => Port(p.info,p.name,p.direction,remove_unknowns(p.tpe)))
             m match {
-               case m:InModule => InModule(m.info,m.name,portsx,m.body)
-               case m:ExModule => ExModule(m.info,m.name,portsx)
+               case m:Module => Module(m.info,m.name,portsx,m.body)
+               case m:ExtModule => ExtModule(m.info,m.name,portsx)
             }
          }
       }
@@ -295,11 +295,11 @@ object ResolveGenders extends Pass {
          m => {
             mname = m.name
             m match {
-               case m:InModule => {
+               case m:Module => {
                   val bodyx = resolve_s(m.body)
-                  InModule(m.info,m.name,m.ports,bodyx)
+                  Module(m.info,m.name,m.ports,bodyx)
                }
-               case m:ExModule => m
+               case m:ExtModule => m
             }
          }
       }
@@ -534,8 +534,8 @@ object InferWidths extends Pass {
          val portsx = m.ports.map{ p => {
             Port(p.info,p.name,p.direction,mapr(reduce_var_widths_w _,p.tpe)) }}
          (m) match {
-            case (m:ExModule) => ExModule(m.info,m.name,portsx)
-            case (m:InModule) => mname = m.name; InModule(m.info,m.name,portsx,mapr(reduce_var_widths_w _,m.body)) }}}
+            case (m:ExtModule) => ExtModule(m.info,m.name,portsx)
+            case (m:Module) => mname = m.name; Module(m.info,m.name,portsx,mapr(reduce_var_widths_w _,m.body)) }}}
       Circuit(c.info,modulesx,c.main)
    }
    
@@ -592,7 +592,7 @@ object InferWidths extends Pass {
 
       for (m <- c.modules) {
          (m) match {
-            case (m:InModule) => mname = m.name; get_constraints(m.body)
+            case (m:Module) => mname = m.name; get_constraints(m.body)
             case (m) => false }}
       //println-debug("======== ALL CONSTRAINTS ========")
       //for x in v do : println-debug(x)
@@ -644,8 +644,8 @@ object PullMuxes extends Pass {
          m => {
             mname = m.name
             m match {
-               case (m:InModule) => InModule(m.info,m.name,m.ports,pull_muxes(m.body))
-               case (m:ExModule) => m
+               case (m:Module) => Module(m.info,m.name,m.ports,pull_muxes(m.body))
+               case (m:ExtModule) => m
             }
          }
       }
@@ -657,7 +657,7 @@ object ExpandConnects extends Pass {
    private var mname = ""
    def name = "Expand Connects"
    def run (c:Circuit): Circuit = {
-      def expand_connects (m:InModule) : InModule = { 
+      def expand_connects (m:Module) : Module = {
          mname = m.name
          val genders = LinkedHashMap[String,Gender]()
          def expand_s (s:Stmt) : Stmt = {
@@ -737,14 +737,14 @@ object ExpandConnects extends Pass {
          }
    
          m.ports.foreach { p => genders(p.name) = to_gender(p.direction) }
-         InModule(m.info,m.name,m.ports,expand_s(m.body))
+         Module(m.info,m.name,m.ports,expand_s(m.body))
       }
    
       val modulesx = c.modules.map { 
          m => {
             m match {
-               case (m:ExModule) => m
-               case (m:InModule) => expand_connects(m)
+               case (m:ExtModule) => m
+               case (m:Module) => expand_connects(m)
             }
          }
       }
@@ -816,7 +816,7 @@ object RemoveAccesses extends Pass {
       ret
    }
    def run (c:Circuit): Circuit = {
-      def remove_m (m:InModule) : InModule = {
+      def remove_m (m:Module) : Module = {
          val namespace = Namespace(m)
          mname = m.name
          def remove_s (s:Stmt) : Stmt = {
@@ -883,14 +883,14 @@ object RemoveAccesses extends Pass {
             stmts += sx
             if (stmts.size != 1) Begin(stmts) else stmts(0)
          }
-         InModule(m.info,m.name,m.ports,remove_s(m.body))
+         Module(m.info,m.name,m.ports,remove_s(m.body))
       }
    
       val modulesx = c.modules.map{
          m => {
             m match {
-               case (m:ExModule) => m
-               case (m:InModule) => remove_m(m)
+               case (m:ExtModule) => m
+               case (m:Module) => remove_m(m)
             }
          }
       }
@@ -946,7 +946,7 @@ object Legalize extends Pass {
       }
       legalizedStmt map legalizeS map legalizeE
     }
-    def legalizeM (m: Module): Module = m map (legalizeS)
+    def legalizeM (m: DefModule): DefModule = m map (legalizeS)
     Circuit(c.info, c.modules.map(legalizeM), c.main)
   }
 }
@@ -983,11 +983,11 @@ object VerilogWrap extends Pass {
    def run (c:Circuit): Circuit = {
       val modulesx = c.modules.map{ m => {
          (m) match {
-            case (m:InModule) => {
+            case (m:Module) => {
                mname = m.name
-               InModule(m.info,m.name,m.ports,v_wrap_s(m.body))
+               Module(m.info,m.name,m.ports,v_wrap_s(m.body))
             }
-            case (m:ExModule) => m
+            case (m:ExtModule) => m
          }
       }}
       Circuit(c.info,modulesx,c.main)
@@ -1014,8 +1014,8 @@ object VerilogRename extends Pass {
             Port(p.info,verilog_rename_n(p.name),p.direction,p.tpe)
          }}
          m match {
-            case (m:InModule) => InModule(m.info,m.name,portsx,verilog_rename_s(m.body))
-            case (m:ExModule) => m
+            case (m:Module) => Module(m.info,m.name,portsx,verilog_rename_s(m.body))
+            case (m:ExtModule) => m
          }
       }}
       Circuit(c.info,modulesx,c.main)
@@ -1041,7 +1041,7 @@ object CInferTypes extends Pass {
       else if (p.direction == INPUT) Field(p.name,REVERSE,p.tpe)
       else error("Shouldn't be here"); Field(p.name,REVERSE,p.tpe)
    }
-   def module_type (m:Module) : Type = BundleType(m.ports.map(p => to_field(p)))
+   def module_type (m:DefModule) : Type = BundleType(m.ports.map(p => to_field(p)))
    def field_type (v:Type,s:String) : Type = {
       (v) match { 
          case (v:BundleType) => {
@@ -1059,7 +1059,7 @@ object CInferTypes extends Pass {
       }
    def run (c:Circuit) : Circuit = {
       val module_types = LinkedHashMap[String,Type]()
-      def infer_types (m:Module) : Module = {
+      def infer_types (m:DefModule) : DefModule = {
          val types = LinkedHashMap[String,Type]()
          def infer_types_e (e:Expression) : Expression = {
             (e map (infer_types_e)) match { 
@@ -1118,8 +1118,8 @@ object CInferTypes extends Pass {
             types(p.name) = p.tpe
          }
          (m) match { 
-            case (m:InModule) => InModule(m.info,m.name,m.ports,infer_types_s(m.body))
-            case (m:ExModule) => m
+            case (m:Module) => Module(m.info,m.name,m.ports,infer_types_s(m.body))
+            case (m:ExtModule) => m
          }
       }
    
@@ -1136,7 +1136,7 @@ object CInferMDir extends Pass {
    def name = "CInfer MDir"
    var mname = ""
    def run (c:Circuit) : Circuit = {
-      def infer_mdir (m:Module) : Module = {
+      def infer_mdir (m:DefModule) : DefModule = {
          val mports = LinkedHashMap[String,MPortDir]()
          def infer_mdir_e (dir:MPortDir)(e:Expression) : Expression = {
             (e map (infer_mdir_e(dir))) match { 
@@ -1196,11 +1196,11 @@ object CInferMDir extends Pass {
             }
          }
          (m) match { 
-            case (m:InModule) => {
+            case (m:Module) => {
                infer_mdir_s(m.body)
-               InModule(m.info,m.name,m.ports,set_mdir_s(m.body))
+               Module(m.info,m.name,m.ports,set_mdir_s(m.body))
             }
-            case (m:ExModule) => m
+            case (m:ExtModule) => m
          }
       }
    
@@ -1237,7 +1237,7 @@ object RemoveCHIRRTL extends Pass {
       }
    }
    def run (c:Circuit) : Circuit = {
-      def remove_chirrtl_m (m:InModule) : InModule = {
+      def remove_chirrtl_m (m:Module) : Module = {
          val hash = LinkedHashMap[String,MPorts]()
          val repl = LinkedHashMap[String,DataRef]()
          val ut = UnknownType()
@@ -1424,12 +1424,12 @@ object RemoveCHIRRTL extends Pass {
          }
          collect_mports(m.body)
          val sx = collect_refs(m.body)
-         InModule(m.info,m.name, m.ports, remove_chirrtl_s(sx))
+         Module(m.info,m.name, m.ports, remove_chirrtl_s(sx))
       }
       val modulesx = c.modules.map{ m => {
             (m) match { 
-               case (m:InModule) => remove_chirrtl_m(m)
-               case (m:ExModule) => m
+               case (m:Module) => remove_chirrtl_m(m)
+               case (m:ExtModule) => m
             }}}
       Circuit(c.info,modulesx, c.main)
    }
diff --git a/src/main/scala/firrtl/passes/RemoveValidIf.scala b/src/main/scala/firrtl/passes/RemoveValidIf.scala
index 4bc6162a..5117caaf 100644
--- a/src/main/scala/firrtl/passes/RemoveValidIf.scala
+++ b/src/main/scala/firrtl/passes/RemoveValidIf.scala
@@ -15,10 +15,10 @@ object RemoveValidIf extends Pass {
    // Recursive.
    private def onStmt(s: Stmt): Stmt = s map onStmt map onExp
 
-   private def onModule(m: Module): Module = {
+   private def onModule(m: DefModule): DefModule = {
       m match {
-         case m:InModule => InModule(m.info, m.name, m.ports, onStmt(m.body))
-         case m:ExModule => m
+         case m: Module => Module(m.info, m.name, m.ports, onStmt(m.body))
+         case m: ExtModule => m
       }
    }
 
diff --git a/src/main/scala/firrtl/passes/SplitExpressions.scala b/src/main/scala/firrtl/passes/SplitExpressions.scala
index a66f7152..4f7fa208 100644
--- a/src/main/scala/firrtl/passes/SplitExpressions.scala
+++ b/src/main/scala/firrtl/passes/SplitExpressions.scala
@@ -10,7 +10,7 @@ import scala.collection.mutable
 //  and named intermediate nodes
 object SplitExpressions extends Pass {
    def name = "Split Expressions"
-   private def onModule(m: InModule): InModule = {
+   private def onModule(m: Module): Module = {
       val namespace = Namespace(m)
       def onStmt(s: Stmt): Stmt = {
          val v = mutable.ArrayBuffer[Stmt]()
@@ -53,12 +53,12 @@ object SplitExpressions extends Pass {
             }
          }
       }
-      InModule(m.info, m.name, m.ports, onStmt(m.body))
+      Module(m.info, m.name, m.ports, onStmt(m.body))
    }
    def run(c: Circuit): Circuit = {
       val modulesx = c.modules.map( _ match {
-         case (m:InModule) => onModule(m)
-         case (m:ExModule) => m
+         case m: Module => onModule(m)
+         case m: ExtModule => m
       })
       Circuit(c.info, modulesx, c.main)
    }
diff --git a/src/main/scala/firrtl/passes/Uniquify.scala b/src/main/scala/firrtl/passes/Uniquify.scala
index 6cec0f1d..9f28f3fa 100644
--- a/src/main/scala/firrtl/passes/Uniquify.scala
+++ b/src/main/scala/firrtl/passes/Uniquify.scala
@@ -258,7 +258,7 @@ object Uniquify extends Pass {
     val portNameMap = collection.mutable.HashMap[String, Map[String, NameMapNode]]()
     val portTypeMap = collection.mutable.HashMap[String, Type]()
 
-    def uniquifyModule(m: Module): Module = {
+    def uniquifyModule(m: DefModule): DefModule = {
       val namespace = collection.mutable.HashSet[String]()
       val nameMap = collection.mutable.HashMap[String, NameMapNode]()
 
@@ -336,8 +336,8 @@ object Uniquify extends Pass {
       sinfo = m.info
       mname = m.name
       m match {
-        case m: ExModule => m
-        case m: InModule =>
+        case m: ExtModule => m
+        case m: Module =>
           // Adds port names to namespace and namemap
           nameMap ++= portNameMap(m.name)
           namespace ++= create_exps("", portTypeMap(m.name)) map
@@ -346,7 +346,7 @@ object Uniquify extends Pass {
       }
     }
 
-    def uniquifyPorts(m: Module): Module = {
+    def uniquifyPorts(m: DefModule): DefModule = {
       def uniquifyPorts(ports: Seq[Port]): Seq[Port] = {
         val portsType = BundleType(ports map (_.toField))
         val uniquePortsType = uniquifyNames(portsType, collection.mutable.HashSet())
@@ -362,8 +362,8 @@ object Uniquify extends Pass {
       sinfo = m.info
       mname = m.name
       m match {
-        case m: ExModule => m.copy(ports = uniquifyPorts(m.ports))
-        case m: InModule => m.copy(ports = uniquifyPorts(m.ports))
+        case m: ExtModule => m.copy(ports = uniquifyPorts(m.ports))
+        case m: Module => m.copy(ports = uniquifyPorts(m.ports))
       }
     }