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2016-02-09Added expand connect. Resolve now includes to working irazidar
2016-02-09Added resolve gendersazidar
2016-02-09WIP. Finished to working ir, resolve kinds, and infer typesazidar
2016-02-09WIP. Got to-working-ir workingazidar
2016-02-09WIP, nothing works. Starting creating working IR and necessary utilsazidar
2016-01-29Fix no space after "flip" for flipped fields in Scala FIRRTL, also make ↵Jack
Scala FIRRTL emission match Stanza FIRRTL for bundles and regs
2016-01-29Changed reg syntax to new "with" semantics in Scala FIRRTLJack
2016-01-28Add support for single-line and multi-line scoping to Scala FIRRTL ↵Jack
preprocessing step. Also added with as scoping keyword
2016-01-28Fixed bug on translating SubAccess concrete syntax to abstract in Scala FIRRTLJack
2016-01-28WIP Added support for mux to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for is invalid and validif to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for stop to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for printf to Scala FIRRTLjackkoenig
2016-01-28WIP: Added support for FIRRTL 0.2.0 Memories to Scala FIRRTLjackkoenig
2016-01-28Move IntLit ANTLR lexer rule to before String lexer rule to ensure IntLit of ↵jackkoenig
form "h..." is lexed as IntLit instead of String
2016-01-28Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtlazidar
2016-01-28Fixed bug where subaccess indexes were being classified as female,azidar
mucking up the chirrtl->firrtl transform. #56.
2016-01-28Changed rmode to wmodeazidar
2016-01-28Use IsInvalid instead of Poisons in chirrtl -> firrtl transformazidar
2016-01-28Fixed bug where you cannot extract from a single bit wire in verilog. #55.azidar
2016-01-28Fixed bug where needed to cast bit-operation inputs prior to verilog emissionazidar
2016-01-28Added addw to working ir as an optimized verilog emissionazidar
2016-01-28Add map of symbol->symbol for wdefinstanceazidar
2016-01-28Fixed matching on types for and, or, and xorazidar
2016-01-28Fixed bug and updated test for changing mod to remazidar
2016-01-28Changed mod to remazidar
2016-01-28Updated with new primops. Removed addw,subw,quo,rem,bit. Added ↵azidar
head,tail,asClock.
2016-01-28Fixed readwriter syntax, and all printed mstats to use => instead of a colonazidar
2016-01-28Changed register syntax for optional reset and init valuesazidar
2016-01-27WIP Moving Scala FIRRTL to match spec 0.2.0. Not everything is implemented ↵jackkoenig
(notably stop, printf, mux, validif, ubits, sbits, readers, writers, and readwriters are incomplete)
2016-01-27Reworked readwriter typesazidar
2016-01-27Fixed additional tests and inferring rdwr ports in chirrtljackkoenig
2016-01-27Merge branch 'scala-new-mem'jackkoenig
2016-01-25Fixed bug where poisons were not being declaredazidar
2016-01-25Added verilog rename passazidar
2016-01-25Added isinvalid and validifazidar
2016-01-25Removed println in expand whenazidar
2016-01-25Fixed width inference bug for muxesazidar
2016-01-25Removed random printlnazidar
2016-01-25Fixed support for muxes and nodes with passive aggregate typesazidar
2016-01-25Changed first generated name to use _0 postfixazidar
2016-01-24Made CInfer robust to high firrtl errorsazidar
2016-01-24Added muxing on passive aggregate typesazidar
2016-01-24Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-memazidar
2016-01-24Removed hashing as it made refchip slower to compileazidar
2016-01-24Added DefMemory to CInfer Typesazidar
2016-01-23Fix Verilog syntax errors for print/stopAndrew Waterman
2016-01-23Removed buggy optimization of dshr and dshlazidar
2016-01-23Moved inst declarations after other declarationsazidar
2016-01-23Fixed commas for instances in verilogazidar
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