Updated with new primops. Removed addw,subw,quo,rem,bit. Added head,tail,asClock.

6 files changed, 206 insertions, 195 deletions

diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 3e388a42..80ae9c08 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -192,38 +192,33 @@ public defn check-high-form (c:Circuit) -> Circuit :
          MUL-OP             : correct-num(2,0)
          DIV-OP             : correct-num(2,0)
          MOD-OP             : correct-num(2,0)
-         QUO-OP             : correct-num(2,0)
-         REM-OP             : correct-num(2,0)
-         ADD-WRAP-OP        : correct-num(2,0)
-         SUB-WRAP-OP        : correct-num(2,0)
          LESS-OP            : correct-num(2,0)
          LESS-EQ-OP         : correct-num(2,0)
          GREATER-OP         : correct-num(2,0)
          GREATER-EQ-OP      : correct-num(2,0)
          EQUAL-OP           : correct-num(2,0)
          NEQUAL-OP          : correct-num(2,0)
-         EQUIV-OP           : correct-num(2,0)
-         NEQUIV-OP          : correct-num(2,0)
-         ;MUX-OP             : correct-num(3,0)
          PAD-OP             : correct-num(1,1)
          AS-UINT-OP         : correct-num(1,0)
          AS-SINT-OP         : correct-num(1,0)
-         DYN-SHIFT-LEFT-OP  : correct-num(2,0)
-         DYN-SHIFT-RIGHT-OP : correct-num(2,0)
+         AS-CLOCK-OP        : correct-num(1,0)
          SHIFT-LEFT-OP      : correct-num(1,1)
          SHIFT-RIGHT-OP     : correct-num(1,1)
+         DYN-SHIFT-LEFT-OP  : correct-num(2,0)
+         DYN-SHIFT-RIGHT-OP : correct-num(2,0)
          CONVERT-OP         : correct-num(1,0)
          NEG-OP             : correct-num(1,0)
-         BIT-NOT-OP         : correct-num(1,0)
-         BIT-AND-OP         : correct-num(2,0)
-         BIT-OR-OP          : correct-num(2,0)
-         BIT-XOR-OP         : correct-num(2,0)
-         BIT-AND-REDUCE-OP  : correct-num(false,0)
-         BIT-OR-REDUCE-OP   : correct-num(false,0)
-         BIT-XOR-REDUCE-OP  : correct-num(false,0)
+         NOT-OP             : correct-num(1,0)
+         AND-OP             : correct-num(2,0)
+         OR-OP              : correct-num(2,0)
+         XOR-OP             : correct-num(2,0)
+         AND-REDUCE-OP      : correct-num(false,0)
+         OR-REDUCE-OP       : correct-num(false,0)
+         XOR-REDUCE-OP      : correct-num(false,0)
          CONCAT-OP          : correct-num(2,0)
-         BIT-SELECT-OP      : correct-num(1,1)
          BITS-SELECT-OP     : correct-num(1,2)
+         HEAD-OP            : correct-num(1,1)
+         TAIL-OP            : correct-num(1,1)
 
    defn check-fstring (s:String,i:Int) -> False :
       val valid-formats = "bedxs"
@@ -481,48 +476,39 @@ defn check-types-primop (e:DoPrim, errors:Vector<PassException>,info:FileInfo) -
             error? = true
       if error? : add(errors,OpNotUInt(info,to-symbol $ op(e),to-symbol(x))) 
    
-   all-ground(args(e))
-
    switch {op(e) == _} :
-      ADD-OP             : false
-      SUB-OP             : false
-      MUL-OP             : false
-      DIV-OP             : false
-      MOD-OP             : false
-      QUO-OP             : false
-      REM-OP             : false
-      ADD-WRAP-OP        : false
-      SUB-WRAP-OP        : false
-      LESS-OP            : false
-      LESS-EQ-OP         : false
-      GREATER-OP         : false
-      GREATER-EQ-OP      : false
-      EQUAL-OP           : false
-      NEQUAL-OP          : false
-      EQUIV-OP           : all-same-type(args(e))
-      NEQUIV-OP          : all-same-type(args(e))
-      ;MUX-OP             : 
-      ;   all-same-type(tail(args(e)))
-      ;   is-uint(head(args(e)))
-      PAD-OP             : false
       AS-UINT-OP         : false
       AS-SINT-OP         : false
-      DYN-SHIFT-LEFT-OP  : is-uint(args(e)[1])
-      DYN-SHIFT-RIGHT-OP : is-uint(args(e)[1])
-      SHIFT-LEFT-OP      : false
-      SHIFT-RIGHT-OP     : false
-      CONVERT-OP         : false
-      NEG-OP             : false
-      BIT-NOT-OP         : all-same-type(args(e)) ;can be either uint or sint
-      BIT-AND-OP         : all-same-type(args(e)) ;can be either uint or sint
-      BIT-OR-OP          : all-same-type(args(e)) ;can be either uint or sint
-      BIT-XOR-OP         : all-same-type(args(e)) ;can be either uint or sint
-      BIT-SELECT-OP      : false ;can be either uint or sint
-      BITS-SELECT-OP     : false ;can be either uint or sint
-      BIT-AND-REDUCE-OP  : false ;can be either uint or sint
-      BIT-OR-REDUCE-OP   : false ;can be either uint or sint
-      BIT-XOR-REDUCE-OP  : false ;can be either uint or sint
-      CONCAT-OP          : false ;can be either uint or sint
+      AS-CLOCK-OP        : false
+      DYN-SHIFT-LEFT-OP  : (is-uint(args(e)[1]) all-ground(args(e)))
+      DYN-SHIFT-RIGHT-OP : (is-uint(args(e)[1]) all-ground(args(e)))
+      ADD-OP             : all-ground(args(e))
+      SUB-OP             : all-ground(args(e))
+      MUL-OP             : all-ground(args(e))
+      DIV-OP             : all-ground(args(e))
+      MOD-OP             : all-ground(args(e))
+      LESS-OP            : all-ground(args(e))
+      LESS-EQ-OP         : all-ground(args(e))
+      GREATER-OP         : all-ground(args(e))
+      GREATER-EQ-OP      : all-ground(args(e))
+      EQUAL-OP           : all-ground(args(e))
+      NEQUAL-OP          : all-ground(args(e))
+      PAD-OP             : all-ground(args(e))
+      SHIFT-LEFT-OP      : all-ground(args(e))
+      SHIFT-RIGHT-OP     : all-ground(args(e))
+      CONVERT-OP         : all-ground(args(e))
+      NEG-OP             : all-ground(args(e))
+      NOT-OP             : all-ground(args(e))
+      AND-OP             : all-ground(args(e))
+      OR-OP              : all-ground(args(e))
+      XOR-OP             : all-ground(args(e))
+      AND-REDUCE-OP      : all-ground(args(e))
+      OR-REDUCE-OP       : all-ground(args(e))
+      XOR-REDUCE-OP      : all-ground(args(e))
+      CONCAT-OP          : all-ground(args(e))
+      BITS-SELECT-OP     : all-ground(args(e))
+      HEAD-OP            : all-ground(args(e))
+      TAIL-OP            : all-ground(args(e))
    
 ;----------------- Check Types Pass ---------------------
 public defn check-types (c:Circuit) -> Circuit : 
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 4d906c70..998c5aa7 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -33,38 +33,33 @@ public val SUB-OP = new PrimOp
 public val MUL-OP = new PrimOp
 public val DIV-OP = new PrimOp
 public val MOD-OP = new PrimOp
-public val QUO-OP = new PrimOp
-public val REM-OP = new PrimOp
-public val ADD-WRAP-OP = new PrimOp
-public val SUB-WRAP-OP = new PrimOp
 public val LESS-OP = new PrimOp
 public val LESS-EQ-OP = new PrimOp
 public val GREATER-OP = new PrimOp
 public val GREATER-EQ-OP = new PrimOp
 public val NEQUAL-OP = new PrimOp
 public val EQUAL-OP = new PrimOp
-public val NEQUIV-OP = new PrimOp
-public val EQUIV-OP = new PrimOp
-;public val MUX-OP = new PrimOp
 public val PAD-OP = new PrimOp
 public val AS-UINT-OP = new PrimOp
 public val AS-SINT-OP = new PrimOp
-public val DYN-SHIFT-LEFT-OP = new PrimOp
-public val DYN-SHIFT-RIGHT-OP = new PrimOp
+public val AS-CLOCK-OP = new PrimOp
 public val SHIFT-LEFT-OP = new PrimOp
 public val SHIFT-RIGHT-OP = new PrimOp
+public val DYN-SHIFT-LEFT-OP = new PrimOp
+public val DYN-SHIFT-RIGHT-OP = new PrimOp
 public val NEG-OP = new PrimOp
 public val CONVERT-OP = new PrimOp
-public val BIT-NOT-OP = new PrimOp
-public val BIT-AND-OP = new PrimOp
-public val BIT-OR-OP = new PrimOp
-public val BIT-XOR-OP = new PrimOp
+public val NOT-OP = new PrimOp
+public val AND-OP = new PrimOp
+public val OR-OP = new PrimOp
+public val XOR-OP = new PrimOp
+public val AND-REDUCE-OP = new PrimOp
+public val OR-REDUCE-OP = new PrimOp
+public val XOR-REDUCE-OP = new PrimOp
 public val CONCAT-OP = new PrimOp
-public val BIT-SELECT-OP = new PrimOp
 public val BITS-SELECT-OP = new PrimOp
-public val BIT-AND-REDUCE-OP = new PrimOp
-public val BIT-OR-REDUCE-OP = new PrimOp
-public val BIT-XOR-REDUCE-OP = new PrimOp
+public val HEAD-OP = new PrimOp
+public val TAIL-OP = new PrimOp
 
 public definterface Expression
 public defmulti type (e:Expression) -> Type
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index bdc1e402..1685996c 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -64,38 +64,34 @@ OPERATORS[`sub] = SUB-OP
 OPERATORS[`mul] = MUL-OP
 OPERATORS[`div] = DIV-OP
 OPERATORS[`mod] = MOD-OP
-OPERATORS[`quo] = QUO-OP
-OPERATORS[`rem] = REM-OP
-OPERATORS[`addw] = ADD-WRAP-OP
-OPERATORS[`subw] = SUB-WRAP-OP
 OPERATORS[`lt] = LESS-OP
 OPERATORS[`leq] = LESS-EQ-OP
 OPERATORS[`gt] = GREATER-OP
 OPERATORS[`geq] = GREATER-EQ-OP
 OPERATORS[`eq] = EQUAL-OP
 OPERATORS[`neq] = NEQUAL-OP
-OPERATORS[`eqv] = EQUIV-OP
-OPERATORS[`neqv] = NEQUIV-OP
-;OPERATORS[`mux] = MUX-OP
 OPERATORS[`pad] = PAD-OP
 OPERATORS[`neg] = NEG-OP
 OPERATORS[`asUInt] = AS-UINT-OP
 OPERATORS[`asSInt] = AS-SINT-OP
-OPERATORS[`dshl] = DYN-SHIFT-LEFT-OP
-OPERATORS[`dshr] = DYN-SHIFT-RIGHT-OP
+OPERATORS[`asClock] = AS-CLOCK-OP
 OPERATORS[`shl] = SHIFT-LEFT-OP
 OPERATORS[`shr] = SHIFT-RIGHT-OP
+OPERATORS[`dshl] = DYN-SHIFT-LEFT-OP
+OPERATORS[`dshr] = DYN-SHIFT-RIGHT-OP
 OPERATORS[`cvt] = CONVERT-OP
-OPERATORS[`andr] = BIT-AND-REDUCE-OP
-OPERATORS[`orr] = BIT-OR-REDUCE-OP
-OPERATORS[`xorr] = BIT-XOR-REDUCE-OP
-OPERATORS[`not] = BIT-NOT-OP
-OPERATORS[`and] = BIT-AND-OP
-OPERATORS[`or] = BIT-OR-OP
-OPERATORS[`xor] = BIT-XOR-OP
+OPERATORS[`neg] = NEG-OP
+OPERATORS[`not] = NOT-OP
+OPERATORS[`and] = AND-OP
+OPERATORS[`or] = OR-OP
+OPERATORS[`xor] = XOR-OP
+OPERATORS[`andr] = AND-REDUCE-OP
+OPERATORS[`orr] = OR-REDUCE-OP
+OPERATORS[`xorr] = XOR-REDUCE-OP
 OPERATORS[`cat] = CONCAT-OP
-OPERATORS[`bit] = BIT-SELECT-OP
 OPERATORS[`bits] = BITS-SELECT-OP
+OPERATORS[`head] = HEAD-OP
+OPERATORS[`tail] = TAIL-OP
 
 ;======== Parser Rules ==================
 defsyntax firrtl :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 009a7db1..1c960974 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -100,17 +100,17 @@ public defn AND (e1:Expression,e2:Expression) -> Expression :
    else if e1 == zero or e2 == zero : zero
    else if e1 == one : e2
    else if e2 == one : e1
-   else : DoPrim(BIT-AND-OP,list(e1,e2),list(),UIntType(IntWidth(1)))
+   else : DoPrim(AND-OP,list(e1,e2),list(),UIntType(IntWidth(1)))
 
 public defn OR (e1:Expression,e2:Expression) -> Expression :
    if e1 == e2 : e1
    else if e1 == one or e2 == one : one
    else if e1 == zero : e2
    else if e2 == zero : e1
-   else : DoPrim(BIT-OR-OP,list(e1,e2),list(),UIntType(IntWidth(1)))
+   else : DoPrim(OR-OP,list(e1,e2),list(),UIntType(IntWidth(1)))
 
 public defn EQV (e1:Expression,e2:Expression) -> Expression :
-   DoPrim(EQUIV-OP,list(e1,e2),list(),type(e1))
+   DoPrim(EQUAL-OP,list(e1,e2),list(),type(e1))
 
 public defn MUX (p:Expression,e1:Expression,e2:Expression) -> Expression :
    Mux(p,e1,e2,mux-type(type(e1),type(e2)))
@@ -134,7 +134,7 @@ public defn CAT (e1:Expression,e2:Expression) -> Expression :
 public defn NOT (e1:Expression) -> Expression :
    if e1 == one : zero
    else if e1 == zero : one
-   else : DoPrim(EQUIV-OP,list(e1,zero),list(),UIntType(IntWidth(1)))
+   else : DoPrim(EQUAL-OP,list(e1,zero),list(),UIntType(IntWidth(1)))
 
 public defn children (e:Expression) -> List<Expression> :
    val es = Vector<Expression>()
@@ -361,38 +361,33 @@ defmethod print (o:OutputStream, op:PrimOp) :
       MUL-OP : "mul"
       DIV-OP : "div"
       MOD-OP : "mod"
-      QUO-OP : "quo"
-      REM-OP : "rem"
-      ADD-WRAP-OP : "addw"
-      SUB-WRAP-OP : "subw"
       LESS-OP : "lt"
       LESS-EQ-OP : "leq"
       GREATER-OP : "gt"
       GREATER-EQ-OP : "geq"
-      EQUIV-OP : "eqv"
-      NEQUIV-OP : "neqv"
       EQUAL-OP : "eq"
       NEQUAL-OP : "neq"
-      ;MUX-OP : "mux"
       PAD-OP : "pad"
       AS-UINT-OP : "asUInt"
       AS-SINT-OP : "asSInt"
-      DYN-SHIFT-LEFT-OP : "dshl"
-      DYN-SHIFT-RIGHT-OP : "dshr"
+      AS-CLOCK-OP : "asClock"
       SHIFT-LEFT-OP : "shl"
       SHIFT-RIGHT-OP : "shr"
+      DYN-SHIFT-LEFT-OP : "dshl"
+      DYN-SHIFT-RIGHT-OP : "dshr"
       CONVERT-OP : "cvt"
       NEG-OP : "neg"
-      BIT-NOT-OP : "not"
-      BIT-AND-OP : "and"
-      BIT-OR-OP : "or"
-      BIT-XOR-OP : "xor"
-      BIT-AND-REDUCE-OP : "andr"
-      BIT-OR-REDUCE-OP : "orr"
-      BIT-XOR-REDUCE-OP : "xorr"
+      NOT-OP : "not"
+      AND-OP : "and"
+      OR-OP : "or"
+      XOR-OP : "xor"
+      AND-REDUCE-OP : "andr"
+      OR-REDUCE-OP : "orr"
+      XOR-REDUCE-OP : "xorr"
       CONCAT-OP : "cat"
-      BIT-SELECT-OP : "bit"
       BITS-SELECT-OP : "bits"
+      HEAD-OP : "head"
+      TAIL-OP : "tail"
    
 defmethod print (o:OutputStream, e:Expression) :
    match(e) :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 68922044..7475e793 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -336,6 +336,8 @@ public defstruct MinusWidth <: Width :
    arg2 : Width
 public defstruct MaxWidth <: Width :
    args : List<Width>
+public defstruct MinWidth <: Width :
+   args : List<Width>
 public defstruct ExpWidth <: Width :
    arg1 : Width
 val width-name-hash = HashTable<Symbol,Int>(symbol-hash)
@@ -344,6 +346,7 @@ public defmulti map<?T> (f: Width -> Width, w:?T&Width) -> T
 defmethod map (f: Width -> Width, w:Width) -> Width :
    match(w) :
       (w:MaxWidth) : MaxWidth(map(f,args(w)))
+      (w:MinWidth) : MinWidth(map(f,args(w)))
       (w:PlusWidth) : PlusWidth(f(arg1(w)),f(arg2(w)))
       (w:MinusWidth) : MinusWidth(f(arg1(w)),f(arg2(w)))
       (w:ExpWidth) : ExpWidth(f(arg1(w)))
@@ -353,6 +356,8 @@ public defmethod print (o:OutputStream, w:VarWidth) :
    print(o,name(w))
 public defmethod print (o:OutputStream, w:MaxWidth) :
    print-all(o,["max" args(w)])
+public defmethod print (o:OutputStream, w:MinWidth) :
+   print-all(o,["min" args(w)])
 public defmethod print (o:OutputStream, w:PlusWidth) :
    print-all(o,[ "(" arg1(w) " + " arg2(w) ")"])
 public defmethod print (o:OutputStream, w:MinusWidth) :
@@ -376,6 +381,13 @@ defmethod equal? (w1:Width,w2:Width) -> True|False :
                for w in args(w1) do :
                   if not contains?(args(w2),w) : ret(false)
                ret(true)
+      (w1:MinWidth,w2:MinWidth) : 
+         label<True|False> ret :
+            if not length(args(w1)) == length(args(w2)) : ret(false)
+            else :
+               for w in args(w1) do :
+                  if not contains?(args(w2),w) : ret(false)
+               ret(true)
       (w1:IntWidth,w2:IntWidth) : width(w1) == width(w2)
       (w1:PlusWidth,w2:PlusWidth) : 
          (arg1(w1) == arg1(w2) and arg2(w1) == arg2(w2)) or (arg1(w1) == arg2(w2) and arg2(w1) == arg1(w2))
@@ -1408,6 +1420,14 @@ defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Width> :
       h
    defn simplify (w:Width) -> Width :
       match(map(simplify,w)) :
+         (w:MinWidth) : 
+            val v = Vector<Width>()
+            for w* in args(w) do :
+               match(w*) :
+                  (w*:MinWidth) : 
+                     for x in args(w*) do : add(v,x)
+                  (w*) : add(v,w*)
+            MinWidth(unique(v))
          (w:MaxWidth) : 
             val v = Vector<Width>()
             for w* in args(w) do :
@@ -1549,6 +1569,9 @@ defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit :
       defn max (a:Long,b:Long) -> Long :
          if a >= b : a
          else : b
+      defn min (a:Long,b:Long) -> Long :
+         if a >= b : b
+         else : a
       defn solve (w:Width) -> False|Long :
          match(w) :
             (w:VarWidth) : 
@@ -1558,6 +1581,7 @@ defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit :
                   (w:False) : false
                   (w) : solve(w as Width)
             (w:MaxWidth) : apply-l(map(solve,args(w)),max)
+            (w:MinWidth) : apply-l(map(solve,args(w)),min)
             (w:PlusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{plus(_,_)})
             (w:MinusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{minus(_,_)})
             (w:ExpWidth) : apply(to-long(2),solve(arg1(w)),{minus(pow(_,_),to-long(1))})
@@ -2016,12 +2040,6 @@ defn const-prop-e (e:Expression) -> Expression :
                      val b = bits(value(x),consts(e)[0] + 1,consts(e)[1])
                      UIntValue(b,width(type(e) as UIntType))
                   (x) : e
-            BIT-SELECT-OP : 
-               match(args(e)[0]) :
-                  (x:UIntValue) : 
-                     val i = bit(value(x),consts(e)[0])
-                     UIntValue(i,width(type(e) as UIntType))
-                  (x) : e
             else : e
       (e) : e
 
@@ -2469,19 +2487,12 @@ defn op-stream (doprim:DoPrim) -> Streamable :
       MUL-OP : [cast-if(a0()) " * " cast-if(a1()) ]
       DIV-OP : [cast-if(a0()) " / " cast-if(a1()) ]
       MOD-OP : [cast-if(a0()) " % " cast-if(a1()) ]
-      QUO-OP : [cast-if(a0()) " / " cast-if(a1()) ]
-      REM-OP : [cast-if(a0()) " % " cast-if(a1()) ]
-      ADD-WRAP-OP : [cast-if(a0()), " + " cast-if(a1())]
-      SUB-WRAP-OP : [cast-if(a0()), " - " cast-if(a1())]
       LESS-OP : [cast-if(a0()) " < " cast-if(a1())]
       LESS-EQ-OP : [cast-if(a0()) " <= " cast-if(a1())]
       GREATER-OP : [cast-if(a0()) " > " cast-if(a1())]
       GREATER-EQ-OP : [cast-if(a0()) " >= " cast-if(a1())]
-      NEQUIV-OP : [cast-if(a0()) " != " cast-if(a1())]
-      EQUIV-OP : [cast-if(a0()) " == " cast-if(a1())]
-      NEQUAL-OP : [cast-if(a0()) " != " cast-if(a1())]
       EQUAL-OP : [cast-if(a0()) " == " cast-if(a1())]
-      ;MUX-OP : [a0() " ? " cast(a1()) " : " cast(a2())]
+      NEQUAL-OP : [cast-if(a0()) " != " cast-if(a1())]
       PAD-OP : 
          val w = long!(type(a0()))
          val diff = (to-long(c0()) - w)
@@ -2491,6 +2502,7 @@ defn op-stream (doprim:DoPrim) -> Streamable :
             (t) : ["{{" diff "'d0 }, " a0() " }"]
       AS-UINT-OP : ["$unsigned(" a0() ")"]
       AS-SINT-OP : ["$signed(" a0() ")"]
+      AS-CLOCK-OP : ["$unsigned(" a0() ")"]
       DYN-SHIFT-LEFT-OP : [cast(a0()) " << " a1()]
       DYN-SHIFT-RIGHT-OP : 
          match(type(doprim)) :
@@ -2503,28 +2515,38 @@ defn op-stream (doprim:DoPrim) -> Streamable :
          match(type(a0())) :
             (t:UIntType) : ["{1'b0," cast(a0()) "}"]
             (t:SIntType) : [cast(a0())]
-      BIT-NOT-OP : ["~ " cast(a0())]
-      BIT-AND-OP : [cast(a0()) " & " cast(a1())]
-      BIT-OR-OP : [cast(a0()) " | " cast(a1())]
-      BIT-XOR-OP : [cast(a0()) " ^ " cast(a1())]
-      CONCAT-OP : ["{" cast(a0()) "," cast(a1()) "}"]
-      BIT-SELECT-OP : [a0() "[" c0() "]"]
-      BITS-SELECT-OP : [a0() "[" c0() ":" c1() "]"]
-      BIT-AND-REDUCE-OP : 
+      NOT-OP : ["~ " cast(a0())]
+      AND-OP : [cast(a0()) " & " cast(a1())]
+      OR-OP : [cast(a0()) " | " cast(a1())]
+      XOR-OP : [cast(a0()) " ^ " cast(a1())]
+      AND-REDUCE-OP : 
          val v = Vector<Streamable>()
          for b in 0 to to-int(long!(type(doprim))) do :
             add(v,[cast(a0()) "[" b "]"])
          join(v," & ")
-      BIT-OR-REDUCE-OP : 
+      OR-REDUCE-OP : 
          val v = Vector<Streamable>()
          for b in 0 to to-int(long!(type(doprim))) do :
             add(v,[cast(a0() ) "[" b "]"])
          join(v," | ")
-      BIT-XOR-REDUCE-OP : 
+      XOR-REDUCE-OP : 
          val v = Vector<Streamable>()
          for b in 0 to to-int(long!(type(doprim))) do :
             add(v,[cast(a0() ) "[" b "]"])
          join(v," ^ ")
+      CONCAT-OP : ["{" cast(a0()) "," cast(a1()) "}"]
+      BITS-SELECT-OP :
+         if c0() == c1() : [a0() "[" c0() "]"]
+         else : [a0() "[" c0() ":" c1() "]"]
+      HEAD-OP :
+         val w = long!(type(a0()))
+         val high = w - to-long(1)
+         val low = w - to-long(c0())
+         [a0() "[" high ":" low "]"]
+      TAIL-OP :
+         val w = long!(type(a0()))
+         val low = w - to-long(c0()) - to-long(1)
+         [a0() "[" low ":" 0 "]"]
 
 defn emit-verilog (m:InModule) -> Module :
    mname = name(m)
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza
index 4b8d0cbc..b6e81be1 100644
--- a/src/main/stanza/primop.stanza
+++ b/src/main/stanza/primop.stanza
@@ -12,6 +12,7 @@ public defn set-primop-type (e:DoPrim) -> DoPrim :
    defn MAX (w1:Width,w2:Width) -> Width : MaxWidth(list(w1,w2))
    defn MINUS (w1:Width,w2:Width) -> Width : MinusWidth(w1,w2)
    defn POW (w1:Width) -> Width : ExpWidth(w1)
+   defn MIN (w1:Width,w2:Width) -> Width : MinWidth(list(w1,w2))
    val o = op(e)
    val a = args(e)
    val c = consts(e)
@@ -38,20 +39,6 @@ public defn set-primop-type (e:DoPrim) -> DoPrim :
             (t1:SIntType, t2:UIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE))
             (t1:SIntType, t2:SIntType) : SIntType(PLUS(MAX(w1(),w2()),ONE))
             (t1, t2) : UnknownType()
-      ADD-WRAP-OP : DoPrim{o,a,c,_} $
-         match(t1(),t2()) :
-            (t1:UIntType, t2:UIntType) : UIntType(MAX(w1(),w2()))
-            (t1:UIntType, t2:SIntType) : SIntType(MAX(w1(),w2()))
-            (t1:SIntType, t2:UIntType) : SIntType(MAX(w1(),w2()))
-            (t1:SIntType, t2:SIntType) : SIntType(MAX(w1(),w2()))
-            (t1, t2) : UnknownType()
-      SUB-WRAP-OP : DoPrim{o,a,c,_} $
-         match(t1(),t2()) :
-            (t1:UIntType, t2:UIntType) : UIntType(MAX(w1(),w2()))
-            (t1:UIntType, t2:SIntType) : SIntType(MAX(w1(),w2()))
-            (t1:SIntType, t2:UIntType) : SIntType(MAX(w1(),w2()))
-            (t1:SIntType, t2:SIntType) : SIntType(MAX(w1(),w2()))
-            (t1, t2) : UnknownType()
       MUL-OP : DoPrim{o,a,c,_} $
          match(t1(),t2()) :
             (t1:UIntType, t2:UIntType) : UIntType(PLUS(w1(),w2()))
@@ -62,58 +49,63 @@ public defn set-primop-type (e:DoPrim) -> DoPrim :
       DIV-OP : DoPrim{o,a,c,_} $
          match(t1(),t2()) :
             (t1:UIntType, t2:UIntType) : UIntType(w1())
-            (t1:UIntType, t2:SIntType) : SIntType(PLUS(w1(),w2()))
+            (t1:UIntType, t2:SIntType) : SIntType(PLUS(w1(),ONE))
             (t1:SIntType, t2:UIntType) : SIntType(w1())
-            (t1:SIntType, t2:SIntType) : SIntType(PLUS(w1(),w2()))
+            (t1:SIntType, t2:SIntType) : SIntType(PLUS(w1(),ONE))
             (t1, t2) : UnknownType()
       MOD-OP : DoPrim{o,a,c,_} $
          match(t1(),t2()) :
-            (t1:UIntType, t2:UIntType) : UIntType(w2())
-            (t1:UIntType, t2:SIntType) : UIntType(w2())
-            (t1:SIntType, t2:UIntType) : SIntType(PLUS(w2(),ONE))
-            (t1:SIntType, t2:SIntType) : SIntType(w2())
+            (t1:UIntType, t2:UIntType) : UIntType(MIN(w1(),w2()))
+            (t1:UIntType, t2:SIntType) : UIntType(MIN(w1(),w2()))
+            (t1:SIntType, t2:UIntType) : SIntType(MIN(w1(),PLUS(w2(),ONE)))
+            (t1:SIntType, t2:SIntType) : SIntType(MIN(w1(),w2()))
+            (t1, t2) : UnknownType()
+      LESS-OP : DoPrim{o,a,c,_} $
+         match(t1(),t2()) :
+            (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType()
             (t1, t2) : UnknownType()
-      QUO-OP : DoPrim{o,a,c,_} $
+      LESS-EQ-OP : DoPrim{o,a,c,_} $
          match(t1(),t2()) :
-            (t1:UIntType, t2:UIntType) : UIntType(PLUS(w1(),ONE))
-            (t1:UIntType, t2:SIntType) : SIntType(w1())
-            (t1:SIntType, t2:UIntType) : SIntType(PLUS(w1(),ONE))
-            (t1:SIntType, t2:SIntType) : SIntType(w1())
+            (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType()
             (t1, t2) : UnknownType()
-      REM-OP : DoPrim{o,a,c,_} $
+      GREATER-OP : DoPrim{o,a,c,_} $
          match(t1(),t2()) :
-            (t1:UIntType, t2:UIntType) : UIntType(w2())
-            (t1:UIntType, t2:SIntType) : SIntType(w2())
-            (t1:SIntType, t2:UIntType) : UIntType(PLUS(w2(),ONE))
-            (t1:SIntType, t2:SIntType) : SIntType(w2())
+            (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType()
+            (t1, t2) : UnknownType()
+      GREATER-EQ-OP : DoPrim{o,a,c,_} $
+         match(t1(),t2()) :
+            (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType()
+            (t1, t2) : UnknownType()
+      EQUAL-OP : DoPrim{o,a,c,_} $
+         match(t1(),t2()) :
+            (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType()
+            (t1, t2) : UnknownType()
+      NEQUAL-OP : DoPrim{o,a,c,_} $
+         match(t1(),t2()) :
+            (t1:UIntType|SIntType, t2:UIntType|SIntType) : BoolType()
             (t1, t2) : UnknownType()
-      LESS-OP : DoPrim(o,a,c,BoolType())
-      LESS-EQ-OP : DoPrim(o,a,c,BoolType())
-      GREATER-OP : DoPrim(o,a,c,BoolType())
-      GREATER-EQ-OP : DoPrim(o,a,c,BoolType())
-      EQUAL-OP : DoPrim(o,a,c,BoolType())
-      NEQUAL-OP : DoPrim(o,a,c,BoolType())
-      EQUIV-OP : DoPrim(o,a,c,BoolType())
-      NEQUIV-OP : DoPrim(o,a,c,BoolType())
-      ;MUX-OP : DoPrim{o,a,c,_} $
-      ;   match(t2(),t3()) :
-      ;      (t2:UIntType, t3:UIntType) : UIntType(MAX(w2(),w3()))
-      ;      (t2:SIntType, t3:SIntType) : SIntType(MAX(w2(),w3()))
-      ;      (t2, t3) : UnknownType()
       PAD-OP : DoPrim{o,a,c,_} $
          match(t1()) :
-            (t1:UIntType) : UIntType(c1())
-            (t1:SIntType) : SIntType(c1())
+            (t1:UIntType) : UIntType(MAX(w1(),c1()))
+            (t1:SIntType) : SIntType(MAX(w1(),c1()))
             (t1) : UnknownType()
       AS-UINT-OP : DoPrim{o,a,c,_} $
          match(t1()) :
             (t1:UIntType) : UIntType(w1())
             (t1:SIntType) : UIntType(w1())
+            (t1:ClockType) : UIntType(ONE)
             (t1) : UnknownType()
       AS-SINT-OP : DoPrim{o,a,c,_} $
          match(t1()) :
             (t1:UIntType) : SIntType(w1())
             (t1:SIntType) : SIntType(w1())
+            (t1:ClockType) : SIntType(ONE)
+            (t1) : UnknownType()
+      AS-CLOCK-OP : DoPrim{o,a,c,_} $
+         match(t1()) :
+            (t1:UIntType) : ClockType()
+            (t1:SIntType) : ClockType()
+            (t1:ClockType) : ClockType()
             (t1) : UnknownType()
       SHIFT-LEFT-OP : DoPrim{o,a,c,_} $
          match(t1()) :
@@ -143,30 +135,55 @@ public defn set-primop-type (e:DoPrim) -> DoPrim :
       NEG-OP : DoPrim{o,a,c,_} $
          match(t1()) :
             (t1:UIntType) : SIntType(PLUS(w1(),ONE))
-            (t1:SIntType) : SIntType(w1())
+            (t1:SIntType) : SIntType(PLUS(w1(),ONE))
             (t1) : UnknownType()
-      BIT-NOT-OP : DoPrim(o,a,c,t1())
-      BIT-AND-OP : DoPrim{o,a,c,_} $
+      NOT-OP : DoPrim{o,a,c,_} $
+         match(t1()) :
+            (t1:UIntType|SIntType) : UIntType(w1())
+            (t1) : UnknownType()
+      AND-OP : DoPrim{o,a,c,_} $
          match(t1()) :
             (t1:UIntType) : UIntType(MAX(w1(),w2()))
-            (t1:SIntType) : SIntType(MAX(w1(),w2()))
+            (t1:SIntType) : UIntType(MAX(w1(),w2()))
             (t1) : UnknownType()
-      BIT-OR-OP : DoPrim{o,a,c,_} $
+      OR-OP : DoPrim{o,a,c,_} $
          match(t1()) :
             (t1:UIntType) : UIntType(MAX(w1(),w2()))
-            (t1:SIntType) : SIntType(MAX(w1(),w2()))
+            (t1:SIntType) : UIntType(MAX(w1(),w2()))
             (t1) : UnknownType()
-      BIT-XOR-OP : DoPrim{o,a,c,_} $
+      XOR-OP : DoPrim{o,a,c,_} $
          match(t1()) :
             (t1:UIntType) : UIntType(MAX(w1(),w2()))
-            (t1:SIntType) : SIntType(MAX(w1(),w2()))
-            (t1) : UnknownType()
-      BIT-AND-REDUCE-OP : DoPrim(o,a,c,BoolType())
-      BIT-OR-REDUCE-OP : DoPrim(o,a,c,BoolType())
-      BIT-XOR-REDUCE-OP : DoPrim(o,a,c,BoolType())
-      CONCAT-OP : DoPrim(o,a,c,UIntType(PLUS(w1(),w2())))
-      BIT-SELECT-OP : DoPrim(o,a,c,BoolType())
-      BITS-SELECT-OP : DoPrim(o,a,c,UIntType(PLUS(MINUS(c1(),c2()),ONE)))
+            (t1:SIntType) : UIntType(MAX(w1(),w2()))
+            (t1) : UnknownType()
+      AND-REDUCE-OP : DoPrim{o,a,c,_} $
+         match(t1()) :
+            (t1:UIntType|SIntType) : BoolType()
+            (t1) : UnknownType()
+      OR-REDUCE-OP : DoPrim{o,a,c,_} $
+         match(t1()) :
+            (t1:UIntType|SIntType) : BoolType()
+            (t1) : UnknownType()
+      XOR-REDUCE-OP : DoPrim{o,a,c,_} $
+         match(t1()) :
+            (t1:UIntType|SIntType) : BoolType()
+            (t1) : UnknownType()
+      CONCAT-OP : DoPrim{o,a,c,_} $
+         match(t1(),t2()) :
+            (t1:UIntType|SIntType, t2:UIntType|SIntType) : UIntType(PLUS(w1(),w2()))
+            (t1, t2) : UnknownType()
+      BITS-SELECT-OP : DoPrim{o,a,c,_} $
+         match(t1()) :
+            (t1:UIntType|SIntType) : UIntType(PLUS(MINUS(c1(),c2()),ONE))
+            (t1) : UnknownType()
+      HEAD-OP : DoPrim{o,a,c,_} $
+         match(t1()) :
+            (t1:UIntType|SIntType) : UIntType(c1())
+            (t1) : UnknownType()
+      TAIL-OP : DoPrim{o,a,c,_} $
+         match(t1()) :
+            (t1:UIntType|SIntType) : UIntType(MINUS(w1(),c1()))
+            (t1) : UnknownType()
 
 ;public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type :
 ;   defn get-max (i0:Int,i1:Int) -> Width : get-max(list(i0,i1))