Added isinvalid and validif

6 files changed, 143 insertions, 17 deletions

diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza
index 684ad53c..f9971323 100644
--- a/src/main/stanza/chirrtl.stanza
+++ b/src/main/stanza/chirrtl.stanza
@@ -100,6 +100,7 @@ defn infer-types (c:Circuit) -> Circuit :
             (e:SubAccess) : SubAccess(exp(e),index(e),sub-type(type(exp(e))))
             (e:DoPrim) : set-primop-type(e)
             (e:Mux) : Mux(cond(e),tval(e),fval(e),mux-type(tval(e),tval(e)))
+            (e:ValidIf) : ValidIf(cond(e),value(e),type(value(e)))
             (e:UIntValue|SIntValue) : e
       defn infer-types-s (s:Stmt) -> Stmt :
          match(s) :
@@ -225,6 +226,9 @@ defn create-exps (e:Expression) -> List<Expression> :
       (e:Mux) :
          for (e1 in create-exps(tval(e)), e2 in create-exps(fval(e))) map :
             Mux(cond(e),e1,e2,mux-type(e1,e2))
+      (e:ValidIf) :
+         for e1 in create-exps(value(e)) map :
+            ValidIf(cond(e),e1,type(e1))
       (e) :
       match(type(e)) : 
          (t:UIntType|SIntType|ClockType) : list(e)
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 1ebe5299..3e388a42 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -262,7 +262,7 @@ public defn check-high-form (c:Circuit) -> Circuit :
       defn check-high-form-e (e:Expression) -> Expression :
          defn valid-subexp (e:Expression) -> Expression :
             match(e) :
-               (e:Ref|SubField|SubIndex|SubAccess|Mux) : false
+               (e:Ref|SubField|SubIndex|SubAccess|Mux|ValidIf) : false
                (e) : add(errors,InvalidAccess())
             e
          match(map(check-high-form-e,e)) :
@@ -270,7 +270,7 @@ public defn check-high-form (c:Circuit) -> Circuit :
                if not key?(names,name(e)) : 
                   add(errors,UndeclaredReference(name(e)))
             (e:DoPrim) : check-high-form-primop(e)
-            (e:Mux) : e
+            (e:Mux|ValidIf) : e
             (e:UIntValue) : false
             (e:SubAccess) : 
                valid-subexp(exp(e))
@@ -427,6 +427,14 @@ defn MuxCondUInt (info:FileInfo) :
    PassException $ string-join $
    [info ": [module " mname "]  A mux condition must be of type UInt."]
 
+defn ValidIfPassiveTypes (info:FileInfo) :
+   PassException $ string-join $
+   [info ": [module " mname "]  Must validif a passive type."]
+
+defn ValidIfCondUInt (info:FileInfo) :
+   PassException $ string-join $
+   [info ": [module " mname "]  A validif condition must be of type UInt."]
+
 ;---------------- Helper Functions --------------
 defmethod equal? (t1:Type,t2:Type) -> True|False :
    match(t1,t2) : 
@@ -557,6 +565,9 @@ public defn check-types (c:Circuit) -> Circuit :
             if not passive?(type(e)) : add(errors,MuxPassiveTypes(info))
             if not passive?(type(e)) : add(errors,MuxPassiveTypes(info))
             if not (type(cond(e)) typeof UIntType) : add(errors,MuxCondUInt(info))
+         (e:ValidIf) :
+            if not passive?(type(e)) : add(errors,ValidIfPassiveTypes(info))
+            if not (type(cond(e)) typeof UIntType) : add(errors,ValidIfCondUInt(info))
          (e:UIntValue|SIntValue) : false
       e
 
@@ -698,6 +709,7 @@ public defn check-genders (c:Circuit) -> Circuit :
          (e:UIntValue) : MALE
          (e:SIntValue) : MALE
          (e:Mux) : MALE
+         (e:ValidIf) : MALE
 
    defn check-genders-e (info:FileInfo,e:Expression,genders:HashTable<Symbol,Gender>) -> False :
       do(check-genders-e{info,_,genders},e)
@@ -710,6 +722,7 @@ public defn check-genders (c:Circuit) -> Circuit :
             for e in args(e) do :
                check-gender(info,genders,e,MALE)
          (e:Mux) : do(check-gender{info,genders,_,MALE},e)
+         (e:ValidIf) : do(check-gender{info,genders,_,MALE},e)
          (e:UIntValue) : false
          (e:SIntValue) : false
      
@@ -723,7 +736,7 @@ public defn check-genders (c:Circuit) -> Circuit :
          (s:DefNode) : 
             check-gender(info(s),genders,value(s),MALE)
             genders[name(s)] = MALE
-         (s:DefMemory) : genders[name(s)] = FEMALE
+         (s:DefMemory) : genders[name(s)] = MALE
          (s:WDefInstance) : genders[name(s)] = MALE
          (s:Connect) : 
             check-gender(info(s),genders,loc(s),FEMALE)
@@ -742,7 +755,7 @@ public defn check-genders (c:Circuit) -> Circuit :
          (s:Stop) : 
             check-gender(info(s),genders,en(s),MALE)
             check-gender(info(s),genders,clk(s),MALE)
-         (s:Begin) : false
+         (s:Begin|IsInvalid) : false
 
    for m in modules(c) do :
       mname = name(m)
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 6a69b9ac..4d906c70 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -89,6 +89,10 @@ public defstruct Mux <: Expression :
    tval: Expression
    fval: Expression
    type: Type with: (as-method => true)
+public defstruct ValidIf <: Expression :
+   cond: Expression
+   value: Expression
+   type: Type with: (as-method => true)
 public defstruct UIntValue <: Expression :
    value: BigInt
    width: Width
@@ -152,6 +156,9 @@ public defstruct Connect <: Stmt : ;LOW
    info: FileInfo with: (as-method => true)
    loc: Expression
    exp: Expression
+public defstruct IsInvalid <: Stmt : ;LOW
+   info: FileInfo with: (as-method => true)
+   exp: Expression
 public defstruct Stop <: Stmt : ;LOW
    info: FileInfo with: (as-method => true)
    ret: Int
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 5d5d56ec..e1083d50 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -297,6 +297,7 @@ defsyntax firrtl :
 
       stmt = (?x:#exp <= ?y:#exp!) : Connect(first-info(form),x, y) ;>
       stmt = (?x:#exp <- ?y:#exp!) : BulkConnect(first-info(form),x, y);>
+      stmt = (?x:#exp is invalid) : IsInvalid(first-info(form),x)
 
       ;stmt = ((?s:#stmt ?rest ...)) :
       ;   Begin(List(s, parse-stmts(rest)))
@@ -367,6 +368,8 @@ defsyntax firrtl :
 
       expterm = (mux(?cond:#exp ?tval:#exp ?fval:#exp)) :
          Mux(cond,tval,fval,UnknownType())
+      expterm = (validif(?cond:#exp ?value:#exp)) :
+         ValidIf(cond,value,UnknownType())
       expterm = (?op:#sym(?es:#exp ... ?ints:#int ... ?rest ...)) :
          if not empty?(rest) :
             FPE(rest, "Illegal operands to primitive operator.")
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index aa98b914..7d4c30b2 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -199,14 +199,14 @@ public defmethod get-type (s:Stmt) -> Type :
 
          val mem-fields = Vector<Field>()
          for x in readers(s) do :
-            add(mem-fields,Field(x,DEFAULT,read-type))
+            add(mem-fields,Field(x,REVERSE,read-type))
          for x in writers(s) do :
-            add(mem-fields,Field(x,DEFAULT,write-type))
+            add(mem-fields,Field(x,REVERSE,write-type))
          for x in readwriters(s) do :
-            add(mem-fields,Field(x,DEFAULT,readwrite-type))
+            add(mem-fields,Field(x,REVERSE,readwrite-type))
          BundleType(to-list(mem-fields))
       (s:DefInstance) : UnknownType()
-      (s:Begin|Connect|BulkConnect|Stop|Print|Empty) : UnknownType()
+      (s:Begin|Connect|BulkConnect|Stop|Print|Empty|IsInvalid) : UnknownType()
      
 public defn get-size (t:Type) -> Int :
    val x = match(t) :
@@ -413,6 +413,8 @@ defmethod print (o:OutputStream, e:Expression) :
          print(o, ")")
       (e:Mux) :
          print-all(o, ["mux(" cond(e) ", " tval(e) ", " fval(e) ")"])
+      (e:ValidIf) :
+         print-all(o, ["validif(" cond(e) ", " value(e) ")"])
    print-debug(o,e)
 
 defmethod print (o:OutputStream, c:Stmt) :
@@ -455,6 +457,8 @@ defmethod print (o:OutputStream, c:Stmt) :
          do(print{o,_}, join(body(c), "\n"))
       (c:Connect) :
          print-all(o, [loc(c) " <= " exp(c)])
+      (c:IsInvalid) :
+         print-all(o, [exp(c) " is invalid"])
       (c:BulkConnect) :
          print-all(o, [loc(c) " <- " exp(c)])
       (c:Empty) :
@@ -545,6 +549,7 @@ defmethod map (f: Expression -> Expression, e:Expression) -> Expression :
       (e:SubAccess) : SubAccess(f(exp(e)), f(index(e)), type(e)) 
       (e:DoPrim) : DoPrim(op(e), map(f, args(e)), consts(e), type(e))
       (e:Mux) : Mux(f(cond(e)),f(tval(e)),f(fval(e)),type(e))
+      (e:ValidIf) : ValidIf(f(cond(e)),f(value(e)),type(e))
       (e) : e
 
 public defmulti map<?T> (f: Symbol -> Symbol, c:?T&Stmt) -> T
@@ -567,6 +572,7 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
       (c:Conditionally) : Conditionally(info(c),f(pred(c)), conseq(c), alt(c))
       (c:Connect) : Connect(info(c),f(loc(c)), f(exp(c)))
       (c:BulkConnect) : BulkConnect(info(c),f(loc(c)), f(exp(c)))
+      (c:IsInvalid) : IsInvalid(info(c),f(exp(c)))
       (c:Stop) : Stop(info(c),ret(c),f(clk(c)),f(en(c)))
       (c:Print) : Print(info(c),string(c),map(f,args(c)),f(clk(c)),f(en(c)))
       (c) : c
@@ -601,6 +607,7 @@ defmethod map (f: Type -> Type, c:Expression) -> Expression :
       (c:SubAccess) : SubAccess(exp(c),index(c),f(type(c)))
       (c:DoPrim) : DoPrim(op(c),args(c),consts(c),f(type(c)))
       (c:Mux) : Mux(cond(c),tval(c),fval(c),f(type(c)))
+      (c:ValidIf) : ValidIf(cond(c),value(c),f(type(c)))
       (c) : c
 
 public defmulti map<?T> (f: Type -> Type, c:?T&Stmt) -> T
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 381ea753..dbb489c4 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -76,6 +76,7 @@ defstruct WIndexer <: Expression :
    type: Type with: (as-method => true)
    gender : Gender with: (as-method => true)
 public defstruct WVoid <: Expression
+public defstruct WInvalid <: Expression
 public defstruct WDefInstance <: Stmt :
    info: FileInfo with: (as-method => true)
    name: Symbol
@@ -90,8 +91,8 @@ defn get-gender (s:Stmt|Port) -> Gender :
    match(s) :
       (s:DefWire|DefRegister) : BI-GENDER
       (s:WDefInstance|DefNode|DefInstance|DefPoison) : MALE
-      (s:Begin|Connect|BulkConnect|Stop|Print|Empty) : UNKNOWN-GENDER
-      (s:DefMemory) : FEMALE
+      (s:Begin|Connect|BulkConnect|Stop|Print|Empty|IsInvalid) : UNKNOWN-GENDER
+      (s:DefMemory) : MALE
       (p:Port) :
          switch { _ == direction(p) } :
             INPUT : MALE
@@ -116,6 +117,7 @@ defmethod info (stmt:Empty) -> FileInfo : FileInfo()
 defmethod type (exp:UIntValue) -> Type : UIntType(width(exp))
 defmethod type (exp:SIntValue) -> Type : SIntType(width(exp))
 defmethod type (exp:WVoid) -> Type : UnknownType()
+defmethod type (exp:WInvalid) -> Type : UnknownType()
 
 defmethod get-type (s:WDefInstance) -> Type : type(s)
 
@@ -135,6 +137,7 @@ defmethod equal? (e1:Expression,e2:Expression) -> True|False :
       (e1:WSubAccess,e2:WSubAccess) : 
          (index(e1) == index(e2)) and (exp(e1) == exp(e2))
       (e1:WVoid,e2:WVoid) : true
+      (e1:WInvalid,e2:WInvalid) : true
       (e1:WIndexer,e2:WIndexer) : 
          var bool = (length(exps(e1)) == length(exps(e2)))
          for (e1* in exps(e1),e2* in exps(e2)) do :
@@ -153,6 +156,9 @@ defmethod equal? (e1:Expression,e2:Expression) -> True|False :
          (cond(e1) == cond(e2)) and 
          (tval(e1) == tval(e2)) and 
          (fval(e1) == fval(e2))
+      (e1:ValidIf,e2:ValidIf) : 
+         (cond(e1) == cond(e2)) and 
+         (value(e1) == value(e2))
       (e1,e2) : false
 
 ; ================= PRINTERS ===================
@@ -287,6 +293,9 @@ defmethod print (o:OutputStream, e:WSubAccess) :
 defmethod print (o:OutputStream, e:WVoid) :
    print(o,"VOID")
    print-debug(o,e as ?)
+defmethod print (o:OutputStream, e:WInvalid) :
+   print(o,"INVALID")
+   print-debug(o,e as ?)
 defmethod print (o:OutputStream, c:WIndexer) :
    print-all(o, [exps(c) "[" index(c) "]"])
    print-debug(o,c as ?)
@@ -692,6 +701,7 @@ defn infer-types (c:Circuit) -> Circuit :
       val types = HashTable<Symbol,Type>(symbol-hash)
       defn infer-types-e (e:Expression) -> Expression :
          match(map(infer-types-e,e)) :
+            (e:ValidIf) : ValidIf(cond(e),value(e),type(value(e)))
             (e:WRef) : WRef(name(e), types[name(e)],kind(e),gender(e))
             (e:WSubField) : WSubField(exp(e),name(e),field-type(type(exp(e)),name(e)),gender(e))
             (e:WSubIndex) : WSubIndex(exp(e),value(e),sub-type(type(exp(e))),gender(e))
@@ -781,6 +791,9 @@ defn resolve-genders (c:Circuit) :
          
    defn resolve-s (s:Stmt) -> Stmt :
       match(s) :
+         (s:IsInvalid) : 
+            val exp* = resolve-e(exp(s),FEMALE)
+            IsInvalid(info(s),exp*)
          (s:Connect) : 
             val loc* = resolve-e(loc(s),FEMALE)
             val exp* = resolve-e(exp(s),MALE)
@@ -814,16 +827,20 @@ defn pull-muxes (c:Circuit) -> Circuit :
          (e:WSubField) :
             match(exp(e)) :
                (e*:Mux) : Mux(cond(e*),WSubField(tval(e*),name(e),type(e),gender(e)),WSubField(fval(e*),name(e),type(e),gender(e)),type(e))
+               (e*:ValidIf) : ValidIf(cond(e*),WSubField(value(e*),name(e),type(e),gender(e)),type(e))
                (e*) : e
          (e:WSubIndex) :
             match(exp(e)) :
                (e*:Mux) : Mux(cond(e*),WSubIndex(tval(e*),value(e),type(e),gender(e)),WSubIndex(fval(e*),value(e),type(e),gender(e)),type(e))
+               (e*:ValidIf) : ValidIf(cond(e*),WSubIndex(value(e*),value(e),type(e),gender(e)),type(e))
                (e*) : e
          (e:WSubAccess) :
             match(exp(e)) :
                (e*:Mux) : Mux(cond(e*),WSubAccess(tval(e*),index(e),type(e),gender(e)),WSubAccess(fval(e*),index(e),type(e),gender(e)),type(e))
+               (e*:ValidIf) : ValidIf(cond(e*),WSubAccess(value(e*),index(e),type(e),gender(e)),type(e))
                (e*) : e
          (e:Mux) : e
+         (e:ValidIf) : e
          (e) : e
                
    defn pull-muxes (s:Stmt) -> Stmt :
@@ -888,6 +905,9 @@ defn create-exps (e:Expression) -> List<Expression> :
       (e:Mux) :
          for (e1 in create-exps(tval(e)), e2 in create-exps(fval(e))) map :
             Mux(cond(e),e1,e2,mux-type-and-widths(e1,e2))
+      (e:ValidIf) :
+         for e1 in create-exps(value(e)) map :
+            ValidIf(cond(e),e1,type(e1))
       (e) :
          match(type(e)) : 
             (t:UIntType|SIntType|ClockType) : list(e)
@@ -919,6 +939,11 @@ defn fast-create-exps (e:Expression) -> List<Expression> :
                Mux(cond(e),e1,e2,mux-type-and-widths(e1,e2))
             hashed-create-exps[e] = x
             x
+         (e:ValidIf) :
+            val x = for e1 in create-exps(value(e)) map :
+               ValidIf(cond(e),e1,type(e1))
+            hashed-create-exps[e] = x
+            x
          (e) : 
             val es = Vector<List<Expression>>()
             match(type(e)) : 
@@ -938,8 +963,41 @@ defn fast-create-exps (e:Expression) -> List<Expression> :
 defn expand-connects (c:Circuit) -> Circuit :
    defn expand-connects (m:InModule) -> InModule :
       mname = name(m)
+      val genders = HashTable<Symbol,Gender>(symbol-hash)
       defn expand-s (s:Stmt) -> Stmt :
+         defn set-gender (e:Expression) -> Expression :
+            match(map(set-gender,e)) :
+               (e:WRef) : WRef(name(e),type(e),kind(e),genders[name(e)])
+               (e:WSubField) : 
+                  val f = {_ as Field} $ 
+                     for f in fields(type(exp(e)) as BundleType) find :
+                        name(f) == name(e)
+                  val gender* = gender(exp(e)) * flip(f) 
+                  WSubField(exp(e),name(e),type(e),gender*)
+               (e:WSubIndex) : WSubIndex(exp(e),value(e),type(e),gender(exp(e)))
+               (e:WSubAccess) : WSubAccess(exp(e),index(e),type(e),gender(exp(e)))
+               (e) : e
          match(s) :
+            (s:DefWire|DefRegister) : 
+               genders[name(s)] = BI-GENDER
+               s
+            (s:WDefInstance|DefMemory|DefPoison|DefNode) : 
+               genders[name(s)] = MALE
+               s
+            (s:IsInvalid) :
+               val n = get-size(exp(s))
+               val invalids = Vector<Stmt>()
+               val exps = create-exps(exp(s))
+               for i in 0 to n do :
+                  val exp* = exps[i]
+                  val gexp* = set-gender(exp*)
+                  switch { _ == gender(gexp*) } :
+                     BI-GENDER : add(invalids,IsInvalid(info(s),exp*))
+                     FEMALE : add(invalids,IsInvalid(info(s),exp*))
+                     else : false
+               if length(invalids) == 0 : Empty()
+               else if length(invalids) == 1 : invalids[0]
+               else : Begin(to-list(invalids))
             (s:Connect) :
                val n = get-size(loc(s))
                val connects = Vector<Stmt>()
@@ -968,6 +1026,8 @@ defn expand-connects (c:Circuit) -> Circuit :
                Begin(to-list(connects))
             (s) : map(expand-s,s)
 
+      for p in ports(m) do :
+         genders[name(p)] = to-gender(direction(p))
       InModule(info(m),name(m),ports(m),expand-s(body(m)))
 
    Circuit(info(c),modules*, main(c)) where :
@@ -1046,6 +1106,7 @@ defn remove-access (c:Circuit) :
             match(e) :
                (e:DoPrim) : map(remove-e,e)
                (e:Mux) : map(remove-e,e)
+               (e:ValidIf) : map(remove-e,e)
                (e:UIntValue|SIntValue) : e
                (e) :
                   if has-access?(e) :
@@ -1153,6 +1214,7 @@ defn expand-whens (c:Circuit) -> Circuit :
       defn expand-whens (s:Stmt,netlist:HashTable<Expression,Expression>,p:Expression) -> Stmt :
          match(s) : 
             (s:Connect) : netlist[loc(s)] = exp(s)
+            (s:IsInvalid) : netlist[exp(s)] = WInvalid()
             (s:Conditionally) :
                val exps = Vector<Expression>()
                defn prefetch (s:Stmt) -> Stmt: 
@@ -1171,7 +1233,12 @@ defn expand-whens (c:Circuit) -> Circuit :
                      (value:Expression) :
                         val tv = c-netlist[lvalue]
                         val fv = value
-                        netlist[lvalue] = Mux(pred(s),tv,fv,mux-type-and-widths(tv,fv))
+                        val res = match(tv,fv) :
+                           (tv:WInvalid,fv:WInvalid) : WInvalid()
+                           (tv:WInvalid,fv) : ValidIf(NOT(pred(s)),fv,type(fv))
+                           (tv,fv:WInvalid) : ValidIf(pred(s),tv,type(tv))
+                           (tv,fv) : Mux(pred(s),tv,fv,mux-type-and-widths(tv,fv))
+                        netlist[lvalue] = res
                      (value:False) :
                         netlist[lvalue] = c-netlist[lvalue]
             (s:Print) : 
@@ -1207,7 +1274,10 @@ defn expand-whens (c:Circuit) -> Circuit :
                   val rvalue = 
                      if s typeof DefRegister : replace-void(e,netlist[e])
                      else : netlist[e]
-                  add(connections,Connect(info(s),e,rvalue))
+                  val con = match(rvalue) :
+                     (rvalue:WInvalid) : IsInvalid(info(s),e)
+                     (rvalue) : Connect(info(s),e,rvalue)
+                  add(connections,con)
             (s:DefPoison|DefNode) : 
                add(stmts,s)
             (s) : map(create,s)
@@ -1215,7 +1285,11 @@ defn expand-whens (c:Circuit) -> Circuit :
       create(body(m))
       for p in ports(m) do :
          for e in get-female-refs(name(p),type(p),get-gender(p)) do :
-            add(connections,Connect(info(p),e,netlist[e]))
+            val rvalue = netlist[e]
+            val con = match(rvalue) :
+               (rvalue:WInvalid) : IsInvalid(info(p),e)
+               (rvalue) : Connect(info(p),e,rvalue)
+            add(connections,con)
       for x in simlist do :
          add(stmts,x)
       InModule(info(m),name(m),ports(m),Begin(list(Begin(to-list(stmts)),Begin(to-list(connections)))))
@@ -2170,6 +2244,7 @@ defn lower-types (m:Module) -> Module :
                   (k) : WRef(lowered-name(e),type(e),kind(e),gender(e))
             (e:DoPrim) : map(lower-types-e,e)
             (e:Mux) : map(lower-types-e,e)
+            (e:ValidIf) : map(lower-types-e,e)
       match(s) :
          (s:DefWire|DefPoison) :
             if is-ground?(type(s)) : s
@@ -2201,6 +2276,13 @@ defn lower-types (m:Module) -> Module :
                val es = create-exps(name(s),data-type(s))
                Begin $ for e in es map :
                   DefMemory(info(s),lowered-name(e),type(e),depth(s),write-latency(s),read-latency(s),readers(s),writers(s),readwriters(s))
+         (s:IsInvalid) : 
+            val s* = map(lower-types-e,s)
+            if kind(exp(s*)) typeof MemKind :
+               val es = lower-mem(exp(s*))
+               Begin $ for e in es map :
+                  IsInvalid(info(s*),e)
+            else : s*
          (s:Connect) :
             val s* = map(lower-types-e,s)
             if kind(loc(s*)) typeof MemKind :
@@ -2277,6 +2359,7 @@ defn long! (t:Type) -> Long :
             w = w + long!(type(f))
          w
       (t:VectorType) : to-long(size(t)) * long!(type(t))
+      (t:ClockType) : to-long(1)
    
 defn rand-string (t:Type) -> Streamable : 
    val w* = ((long!(t) + to-long(31)) / to-long(32))
@@ -2292,8 +2375,8 @@ defn emit (x:?, top:Int) :
          turn-off-debug(false)
          match(e) :
             (e:DoPrim) : emit(op-stream(e), top + 1)
-            (e:Mux) : 
-               emit([cond(e) " ? " cast(tval(e)) " : " cast(fval(e))],top + 1)
+            (e:Mux) : emit([cond(e) " ? " cast(tval(e)) " : " cast(fval(e))],top + 1)
+            (e:ValidIf) : emit([cast(value(e))],top + 1)
             (e:WRef) : print(e)
             (e:WSubField) : print(lowered-name(e))
             (e:WSubAccess) : print-all([lowered-name(exp(e)) "[" lowered-name(index(e)) "]"])
@@ -2422,6 +2505,10 @@ defn emit-verilog (m:InModule) -> Module :
    defn build-netlist (s:Stmt) -> Stmt :
       match(s) :
          (s:Connect) : netlist[loc(s)] = exp(s)
+         (s:IsInvalid) : 
+            val n = firrtl-gensym(`GEN,namehash)
+            val e = wref(n,type(exp(s)))
+            netlist[exp(s)] = e
          (s:Conditionally) : add(simlist,s)
          (s:DefNode) : 
             val e = WRef(name(s),get-type(s),NodeKind(),MALE)
@@ -2531,9 +2618,14 @@ defn emit-verilog (m:InModule) -> Module :
             val e = wref(name(s),type(s))
             update-and-reset(e,clock(s),reset(s),init(s))
             initialize(e)
+         (s:IsInvalid) :
+            val wref = netlist[exp(s)] as WRef
+            declare(`reg,name(wref),type(exp(s)))
+            initialize(wref)
          (s:DefPoison) :
-            declare(`reg,name(s),type(s))
-            val e = wref(name(s),type(s))
+            val n = firrtl-gensym(`GEN,namehash)
+            val e = wref(n,type(s))
+            declare(`reg,n,type(e))
             initialize(e)
          (s:DefNode) :
             declare(`wire,name(s),type(value(s)))