diff options
| author | Jack | 2016-01-29 00:43:53 -0800 |
|---|---|---|
| committer | Jack | 2016-01-29 00:45:07 -0800 |
| commit | 1e094fcfa26e239c37454fe1e79f640d45433174 (patch) | |
| tree | 3804ac6b96814cc8a0d4b13fa5b3eab036d9290a /src | |
| parent | 676fbd9f97fcbedf351a904b645eb200c12144a5 (diff) | |
Fix no space after "flip" for flipped fields in Scala FIRRTL, also make Scala FIRRTL emission match Stanza FIRRTL for bundles and regs
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/Utils.scala | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala index 1a6a7725..ee974f11 100644 --- a/src/main/scala/firrtl/Utils.scala +++ b/src/main/scala/firrtl/Utils.scala @@ -135,8 +135,11 @@ object Utils { var ret = stmt match { case w: DefWire => s"wire ${w.name} : ${w.tpe.serialize}" case r: DefRegister => - s"reg ${r.name} : ${r.tpe.serialize}, ${r.clock.serialize} with : " + - s"(reset => (${r.reset.serialize}, ${r.init.serialize}))" + val str = new StringBuilder(s"reg ${r.name} : ${r.tpe.serialize}, ${r.clock.serialize} with : ") + withIndent { + str ++= newline + s"reset => (${r.reset.serialize}, ${r.init.serialize})" + } + str case i: DefInstance => s"inst ${i.name} of ${i.module}" case m: DefMemory => { val str = new StringBuilder(s"mem ${m.name} : " + newline) @@ -206,7 +209,7 @@ object Utils { implicit class FlipUtils(f: Flip) { def serialize(implicit flags: FlagMap = FlagMap): String = { val s = f match { - case Reverse => "flip" + case Reverse => "flip " case Default => "" } s + debug(f) @@ -244,7 +247,7 @@ object Utils { case UnknownType => "?" case t: UIntType => s"UInt${t.width.serialize}" case t: SIntType => s"SInt${t.width.serialize}" - case t: BundleType => s"{${t.fields.map(_.serialize).mkString(commas)}}" + case t: BundleType => s"{ ${t.fields.map(_.serialize).mkString(commas)}}" case t: VectorType => s"${t.tpe.serialize}[${t.size}]" } s + debug(t) @@ -292,7 +295,7 @@ object Utils { var s = new StringBuilder(s"module ${m.name} : ") withIndent { s ++= m.ports.map(newline ++ _.serialize).mkString - s ++= newline ++ m.stmt.serialize + s ++= m.stmt.serialize } s ++= debug(m) s.toString |
