Changed rmode to wmode

3 files changed, 24 insertions, 18 deletions

diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza
index 9fc471fa..e92cab61 100644
--- a/src/main/stanza/chirrtl.stanza
+++ b/src/main/stanza/chirrtl.stanza
@@ -223,6 +223,7 @@ defstruct DataRef :
    male : Symbol
    female : Symbol
    mask : Symbol
+   rdwrite? : True|False
 
 public definterface Gender
 public val MALE = new Gender
@@ -285,9 +286,9 @@ defn remove-chirrtl (c:Circuit) :
                defn set-enable (vec:List<MPort>,en:Symbol) -> False:
                   for r in vec do :
                      add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),en,taddr),zero))
-               defn set-rmode (vec:List<MPort>,rmode:Symbol) -> False:
+               defn set-wmode (vec:List<MPort>,wmode:Symbol) -> False:
                   for r in vec do :
-                     add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),rmode,taddr),one))
+                     add(stmts,Connect(info(s),SubField(SubField(Ref(name(s),ut),name(r),ut),wmode,taddr),zero))
                defn set-write (vec:List<MPort>,data:Symbol,mask:Symbol) -> False :
                   val tmask = create-mask(type(s))
                   for r in vec do :
@@ -304,7 +305,7 @@ defn remove-chirrtl (c:Circuit) :
                set-write(wrs,`data,`mask)
                val rws = to-list $ readwriters $ get?(hash,name(s),EMPs())
                set-poison(rws,`addr)
-               set-rmode(rws,`rmode)
+               set-wmode(rws,`wmode)
                set-enable(rws,`en)
                set-write(rws,`data,`mask)
                val read-l = 
@@ -317,21 +318,19 @@ defn remove-chirrtl (c:Circuit) :
                val addrs = Vector<Symbol>()
                val ens = Vector<Symbol>()
                val masks = Vector<Symbol>()
-               val rmodes = Vector<Symbol>()
                switch { _ == direction(s) } :
                   MReadWrite : 
-                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`rdata,`data,`mask)
+                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`rdata,`data,`mask,true)
                      add(addrs,`addr)
                      add(ens,`en)
-                     add(rmodes,`rmode)
                      add(masks,`mask)
                   MWrite :
-                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`mask)
+                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`mask,false)
                      add(addrs,`addr)
                      add(ens,`en)
                      add(masks,`mask)
                   else :
-                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`blah)
+                     repl[name(s)] = DataRef(SubField(Ref(mem(s),ut),name(s),ut),`data,`data,`blah,false)
                      add(addrs,`addr)
                      add(ens,`en)
 
@@ -340,12 +339,11 @@ defn remove-chirrtl (c:Circuit) :
                   add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),exps(s)[0]))
                for x in ens do :
                   add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),one))
-               for x in rmodes do :
-                  add(stmts,Connect(info(s),SubField(SubField(Ref(mem(s),ut),name(s),ut),x,ut),zero))
                Begin $ to-list $ stmts
             (s) : map(collect-refs,s)
       defn remove-chirrtl-s (s:Stmt) -> Stmt :
          var has-write-mport? = false
+         var has-readwrite-mport? = false
          defn remove-chirrtl-e (e:Expression,g:Gender) -> Expression :
             match(map(remove-chirrtl-e{_,g},e)) :
                (e:Ref) : 
@@ -355,6 +353,8 @@ defn remove-chirrtl (c:Circuit) :
                         MALE : SubField(exp(vt),male(vt),type(e))
                         FEMALE : 
                            has-write-mport? = true
+                           if rdwrite?(vt) == true :
+                              has-readwrite-mport? = SubField(exp(vt),`wmode,UIntType(IntWidth(1)))
                            SubField(exp(vt),female(vt),type(e))
                   else : e
                (e) : e
@@ -377,6 +377,9 @@ defn remove-chirrtl (c:Circuit) :
                   val e = get-mask(loc(s))
                   for x in create-exps(e) do :
                      add(stmts,Connect(info(s),x,one))
+                  if has-readwrite-mport? != false :
+                     val wmode = has-readwrite-mport? as Expression
+                     add(stmts,Connect(info(s),wmode,one))
                if length(stmts) > 1 : Begin(to-list(stmts))
                else : stmts[0]
             (s:BulkConnect) : 
@@ -384,12 +387,15 @@ defn remove-chirrtl (c:Circuit) :
                val loc* = remove-chirrtl-e(loc(s),FEMALE)
                val roc* = remove-chirrtl-e(exp(s),MALE)
                add(stmts,BulkConnect(info(s),loc*,roc*))
-               if has-write-mport? :
+               if has-write-mport? != false :
                   val ls = get-valid-points(type(loc(s)),type(exp(s)),DEFAULT,DEFAULT)
                   val locs = create-exps(get-mask(loc(s)))
                   for x in ls do :
                      val loc* = locs[x[0]]
                      add(stmts,Connect(info(s),loc*,one))
+                  if has-readwrite-mport? != false :
+                     val wmode = has-readwrite-mport? as Expression
+                     add(stmts,Connect(info(s),wmode,one))
                if length(stmts) > 1 : Begin(to-list(stmts))
                else : stmts[0]
             (s) : map(remove-chirrtl-e{_,MALE}, map(remove-chirrtl-s,s))
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 9fd8b39a..24149649 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -185,12 +185,12 @@ public defmethod get-type (s:Stmt) -> Type :
          val def-data = Field(`data,DEFAULT,data-type(s))
          val rev-data = Field(`data,REVERSE,data-type(s))
          val mask = Field(`mask,DEFAULT,create-mask(data-type(s)))
-         val rmode = Field(`rmode,DEFAULT,UIntType(IntWidth(1)))
+         val wmode = Field(`wmode,DEFAULT,UIntType(IntWidth(1)))
          val rdata = Field(`rdata,REVERSE,data-type(s))
 
          val read-type = BundleType(to-list([rev-data,addr,en,clk]))
          val write-type = BundleType(to-list([def-data,mask,addr,en,clk]))
-         val readwrite-type = BundleType(to-list([rmode,rdata,def-data,mask,addr,en,clk]))
+         val readwrite-type = BundleType(to-list([wmode,rdata,def-data,mask,addr,en,clk]))
 
          val mem-fields = Vector<Field>()
          for x in readers(s) do :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 4824cdca..503e16c4 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2804,7 +2804,7 @@ defn emit-verilog (m:InModule) -> Module :
                update(mem-port,data*,clk,AND(en*,mask*))
 
             for rw in readwriters(s) do :
-               val rmode = mem-exp(rw,`rmode)
+               val wmode = mem-exp(rw,`wmode)
                val rdata = mem-exp(rw,`rdata)
                val data = mem-exp(rw,`data)
                val mask = mem-exp(rw,`mask)
@@ -2812,7 +2812,7 @@ defn emit-verilog (m:InModule) -> Module :
                val en = mem-exp(rw,`en)
                val clk = mem-exp(rw,`clk)
                
-               declare(`wire,lowered-name(rmode),type(rmode))
+               declare(`wire,lowered-name(wmode),type(wmode))
                declare(`wire,lowered-name(rdata),type(rdata))
                declare(`wire,lowered-name(data),type(data))
                declare(`wire,lowered-name(mask),type(mask))
@@ -2827,13 +2827,13 @@ defn emit-verilog (m:InModule) -> Module :
                assign(addr,netlist[addr])
                assign(mask,netlist[mask])
                assign(en,netlist[en])
-               assign(rmode,netlist[rmode])
+               assign(wmode,netlist[wmode])
 
                ; Delay new signals by latency
                val raddr* = delay(addr,read-latency(s),clk)
                val waddr* = delay(addr,write-latency(s) - 1,clk)
                val en* = delay(en,write-latency(s) - 1,clk)
-               val rmod* = delay(rmode,write-latency(s) - 1,clk)
+               val rmod* = delay(wmode,write-latency(s) - 1,clk)
                val data* = delay(data,write-latency(s) - 1,clk)
                val mask* = delay(mask,write-latency(s) - 1,clk)
 
@@ -2842,7 +2842,7 @@ defn emit-verilog (m:InModule) -> Module :
                val rmem-port = WSubAccess(mem,raddr*,UnknownType(),UNKNOWN-GENDER)
                assign(rdata,rmem-port)
                val wmem-port = WSubAccess(mem,waddr*,UnknownType(),UNKNOWN-GENDER)
-               update(wmem-port,data*,clk,AND(AND(en*,mask*),NOT(rmode)))
+               update(wmem-port,data*,clk,AND(AND(en*,mask*),wmode))
          (s:Begin) : map(build-streams,s)
       s