Added resolve genders

5 files changed, 111 insertions, 29 deletions

diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index 7ea0286d..13e47e82 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -84,8 +84,6 @@ object Driver extends LazyLogging {
 // =====================================
     StanzaPass("high-form-check"),
 // =====================================
-    ScalaPass(resolve),
-// =====================================
     StanzaPass("to-working-ir"),
 // =====================================
     StanzaPass("resolve-kinds"),
@@ -96,6 +94,8 @@ object Driver extends LazyLogging {
     StanzaPass("infer-widths"),
     StanzaPass("width-check"),
 // =====================================
+    ScalaPass(resolve),
+// =====================================
     StanzaPass("pull-muxes"),
 // =====================================
     StanzaPass("expand-connects"),
diff --git a/src/main/scala/firrtl/IR.scala b/src/main/scala/firrtl/IR.scala
index c86be37a..a4da76a9 100644
--- a/src/main/scala/firrtl/IR.scala
+++ b/src/main/scala/firrtl/IR.scala
@@ -85,8 +85,8 @@ case class IntWidth(width: BigInt) extends Width
 case class UnknownWidth() extends Width
 
 trait Flip extends AST
-case object Default extends Flip
-case object Reverse extends Flip
+case object DEFAULT extends Flip
+case object REVERSE extends Flip
 
 case class Field(name: String, flip: Flip, tpe: Type) extends AST
 
diff --git a/src/main/scala/firrtl/Passes.scala b/src/main/scala/firrtl/Passes.scala
index 29b42d54..53429389 100644
--- a/src/main/scala/firrtl/Passes.scala
+++ b/src/main/scala/firrtl/Passes.scala
@@ -28,8 +28,8 @@ object Passes extends LazyLogging {
    private def toField(p: Port): Field = {
      logger.debug(s"toField called on port ${p.serialize}")
      p.direction match {
-       case Input  => Field(p.name, Reverse, p.tpe)
-       case Output => Field(p.name, Default, p.tpe)
+       case Input  => Field(p.name, REVERSE, p.tpe)
+       case Output => Field(p.name, DEFAULT, p.tpe)
      }
    }
    // ============== RESOLVE ALL ===================
@@ -37,11 +37,13 @@ object Passes extends LazyLogging {
       val passes = Seq(
          toWorkingIr _,
          resolveKinds _,
-         inferTypes _)
+         inferTypes _,
+         resolveGenders _)
       val names = Seq(
          "To Working IR",
          "Resolve Kinds",
-         "Infer Types")
+         "Infer Types",
+         "Resolve Genders")
       var c_BANG = c
       (names, passes).zipped.foreach { 
          (n,p) => {
@@ -258,6 +260,64 @@ object Passes extends LazyLogging {
       x
    }
 
+   def resolveGenders (c:Circuit) = {
+      def resolve_e (g:Gender)(e:Expression) : Expression = {
+         e match {
+            case e:WRef => WRef(e.name,e.tpe,e.kind,g)
+            case e:WSubField => {
+               val expx = 
+                  field_flip(tpe(e.exp),e.name) match {
+                     case DEFAULT => resolve_e(g)(e.exp)
+                     case REVERSE => resolve_e(swap(g))(e.exp)
+                  }
+               WSubField(expx,e.name,e.tpe,g)
+            }
+            case e:WSubIndex => {
+               val expx = resolve_e(g)(e.exp)
+               WSubIndex(expx,e.value,e.tpe,g)
+            }
+            case e:WSubAccess => {
+               val expx = resolve_e(g)(e.exp)
+               val indexx = resolve_e(MALE)(e.index)
+               WSubAccess(expx,indexx,e.tpe,g)
+            }
+            case e => eMap(resolve_e(g) _,e)
+         }
+      }
+            
+      def resolve_s (s:Stmt) : Stmt = {
+         s match {
+            case s:IsInvalid => {
+               val expx = resolve_e(FEMALE)(s.exp)
+               IsInvalid(s.info,expx)
+            }
+            case s:Connect => {
+               val locx = resolve_e(FEMALE)(s.loc)
+               val expx = resolve_e(MALE)(s.exp)
+               Connect(s.info,locx,expx)
+            }
+            case s:BulkConnect => {
+               val locx = resolve_e(FEMALE)(s.loc)
+               val expx = resolve_e(MALE)(s.exp)
+               BulkConnect(s.info,locx,expx)
+            }
+            case s => sMap(resolve_s,eMap(resolve_e(MALE) _,s))
+         }
+      }
+      val modulesx = c.modules.map { 
+         m => {
+            m match {
+               case m:InModule => {
+                  val bodyx = resolve_s(m.body)
+                  InModule(m.info,m.name,m.ports,bodyx)
+               }
+               case m:ExModule => m
+            }
+         }
+      }
+      Circuit(c.info,modulesx,c.main)
+   }
+
   /** INFER TYPES
    *
    *  This pass infers the type field in all IR nodes by updating
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index f029d410..3b849e45 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -143,8 +143,30 @@ object Utils {
      def serialize(implicit flags: FlagMap = FlagMap): String = op.getString
    }
 
+// =========== GENDER UTILS ============
+   def swap (g:Gender) : Gender = {
+      g match {
+         case UNKNOWNGENDER => UNKNOWNGENDER
+         case MALE => FEMALE
+         case FEMALE => MALE
+         case BIGENDER => BIGENDER
+      }
+   }
+// =========== FLIP UTILS ===============
+   def field_flip (v:Type,s:String) : Flip = {
+      v match {
+         case v:BundleType => {
+            val ft = v.fields.find {p => p.name == s}
+            ft match {
+               case ft:Some[Field] => ft.get.flip
+               case ft => DEFAULT
+            }
+         }
+         case v => DEFAULT
+      }
+   }
 
-//  ACCESSORS =========
+// =========== ACCESSORS =========
    def gender (e:Expression) : Gender = {
      e match {
         case e:WRef => gender(e)
@@ -206,22 +228,22 @@ object Utils {
        case s:DefNode => tpe(s.value)
        case s:DefMemory => {
           val depth = s.depth
-          val addr = Field("addr",Default,UIntType(IntWidth(ceil_log2(depth))))
-          val en = Field("en",Default,BoolType())
-          val clk = Field("clk",Default,ClockType())
-          val def_data = Field("data",Default,s.data_type)
-          val rev_data = Field("data",Reverse,s.data_type)
-          val mask = Field("mask",Default,create_mask(s.data_type))
-          val wmode = Field("wmode",Default,UIntType(IntWidth(1)))
-          val rdata = Field("rdata",Reverse,s.data_type)
+          val addr = Field("addr",DEFAULT,UIntType(IntWidth(ceil_log2(depth))))
+          val en = Field("en",DEFAULT,BoolType())
+          val clk = Field("clk",DEFAULT,ClockType())
+          val def_data = Field("data",DEFAULT,s.data_type)
+          val rev_data = Field("data",REVERSE,s.data_type)
+          val mask = Field("mask",DEFAULT,create_mask(s.data_type))
+          val wmode = Field("wmode",DEFAULT,UIntType(IntWidth(1)))
+          val rdata = Field("rdata",REVERSE,s.data_type)
           val read_type = BundleType(Seq(rev_data,addr,en,clk))
           val write_type = BundleType(Seq(def_data,mask,addr,en,clk))
           val readwrite_type = BundleType(Seq(wmode,rdata,def_data,mask,addr,en,clk))
 
           val mem_fields = Vector()
-          s.readers.foreach {x => mem_fields :+ Field(x,Reverse,read_type)}
-          s.writers.foreach {x => mem_fields :+ Field(x,Reverse,write_type)}
-          s.readwriters.foreach {x => mem_fields :+ Field(x,Reverse,readwrite_type)}
+          s.readers.foreach {x => mem_fields :+ Field(x,REVERSE,read_type)}
+          s.writers.foreach {x => mem_fields :+ Field(x,REVERSE,write_type)}
+          s.readwriters.foreach {x => mem_fields :+ Field(x,REVERSE,readwrite_type)}
           BundleType(mem_fields)
        }
        case s:DefInstance => UnknownType()
@@ -461,22 +483,22 @@ object Utils {
    implicit class FlipUtils(f: Flip) {
      def serialize(implicit flags: FlagMap = FlagMap): String = {
        val s = f match {
-         case Reverse => "flip "
-         case Default => ""
+         case REVERSE => "flip "
+         case DEFAULT => ""
        } 
        s + debug(f)
      }
      def flip(): Flip = {
        f match {
-         case Reverse => Default
-         case Default => Reverse
+         case REVERSE => DEFAULT
+         case DEFAULT => REVERSE
        }
      }
          
      def toDirection(): Direction = {
        f match {
-         case Default => Output
-         case Reverse => Input
+         case DEFAULT => Output
+         case REVERSE => Input
        }
      }
    }
@@ -529,8 +551,8 @@ object Utils {
      }
      def toFlip(): Flip = {
        d match {
-         case Input => Reverse
-         case Output => Default
+         case Input => REVERSE
+         case Output => DEFAULT
        }
      }
    }
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index 42de6348..ccdb2e22 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -71,7 +71,7 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
   }
       
 	private def visitField[AST](ctx: FIRRTLParser.FieldContext): Field = {
-    val flip = if(ctx.getChild(0).getText == "flip") Reverse else Default
+    val flip = if(ctx.getChild(0).getText == "flip") REVERSE else DEFAULT
     Field((ctx.id.getText), flip, visitType(ctx.`type`))
   }