diff options
| author | azidar | 2016-01-23 16:57:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-23 16:57:45 -0800 |
| commit | 725a4a4a313555b1a60e9e8bdd4e99302e6682d0 (patch) | |
| tree | d4362274e3bf27e94aba59b707bf1fe77160a405 /src | |
| parent | fd3941adb86e492ec33bb92e86b18a77367f0f6f (diff) | |
Fixed commas for instances in verilog
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/stanza/passes.stanza | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 38954f4f..150abe32 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -2433,9 +2433,9 @@ defn emit-verilog (m:InModule) -> Module : add(initials,[tab WSubAccess(wref(n,t),index,UnknownType(),FEMALE), " = " rand-string(t) ";"]) defn instantiate (n:Symbol,m:Symbol,es:List<Expression>) : add(declares,[m " " n " ("]) - for (e in es,i in 1 to false) do : + for (e in es,i in 0 to false) do : val s = [tab "." remove-root(e) "(" lowered-name(e) ")"] - if i == length(es) : add(declares,[s ","]) + if i != length(es) - 1 : add(declares,[s ","]) else : add(declares,s) add(declares,[");"]) for e in es do : |