From 725a4a4a313555b1a60e9e8bdd4e99302e6682d0 Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 23 Jan 2016 16:57:45 -0800
Subject: Fixed commas for instances in verilog

---
 src/main/stanza/passes.stanza | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 38954f4f..150abe32 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2433,9 +2433,9 @@ defn emit-verilog (m:InModule) -> Module :
       add(initials,[tab WSubAccess(wref(n,t),index,UnknownType(),FEMALE), " = " rand-string(t) ";"])
    defn instantiate (n:Symbol,m:Symbol,es:List<Expression>) :
       add(declares,[m " " n " ("])
-      for (e in es,i in 1 to false) do :
+      for (e in es,i in 0 to false) do :
          val s = [tab "." remove-root(e) "(" lowered-name(e) ")"]
-         if i == length(es) : add(declares,[s ","])
+         if i != length(es) - 1 : add(declares,[s ","])
          else : add(declares,s)
       add(declares,[");"])
       for e in es do :
-- 
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