WIP, nothing works. Starting creating working IR and necessary utils

6 files changed, 139 insertions, 105 deletions

diff --git a/src/main/scala/firrtl/Driver.scala b/src/main/scala/firrtl/Driver.scala
index 34a69110..3eee19bd 100644
--- a/src/main/scala/firrtl/Driver.scala
+++ b/src/main/scala/firrtl/Driver.scala
@@ -76,46 +76,52 @@ object Driver extends LazyLogging {
   }
 
   val defaultPasses = DriverPasses.optimize(Seq(
-    StanzaPass("to-firrtl"),
-
+    StanzaPass("cinfertypes"),
+// =====================================
+    StanzaPass("cinfermdir"),
+// =====================================
+    StanzaPass("removechirrtl"),
+// =====================================
     StanzaPass("high-form-check"),
-
-//  ScalaPass(renameall(Map(
-//    "c"->"ccc",
-//    "z"->"zzz",
-//    "top"->"its_a_top_module"
-//  ))),
-    // StanzaPass("temp-elim"), // performance pass
+// =====================================
     StanzaPass("to-working-ir"),
-
+// =====================================
     StanzaPass("resolve-kinds"),
-    StanzaPass("infer-types"),
+//    StanzaPass("infer-types"),
+    ScalaPass(inferTypes),
     StanzaPass("check-types"),
     StanzaPass("resolve-genders"),
     StanzaPass("check-genders"),
     StanzaPass("infer-widths"),
     StanzaPass("width-check"),
-
-    StanzaPass("check-kinds"),
-
-    StanzaPass("expand-accessors"),
-    StanzaPass("lower-to-ground"),
-    StanzaPass("inline-indexers"),
-    StanzaPass("infer-types"),
-    //ScalaPass(inferTypes),
-    StanzaPass("check-genders"),
+// =====================================
+    StanzaPass("pull-muxes"),
+// =====================================
+    StanzaPass("expand-connects"),
+// =====================================
+    StanzaPass("remove-access"),
+// =====================================
     StanzaPass("expand-whens"),
-
-    StanzaPass("real-ir"),
-
-    StanzaPass("pad-widths"),
+// =====================================
+    StanzaPass("check-init"),
+// =====================================
     StanzaPass("const-prop"),
-    StanzaPass("split-expressions"),
-    StanzaPass("width-check"),
-    StanzaPass("high-form-check"),
-    StanzaPass("low-form-check"),
-    StanzaPass("check-init")//,
+// =====================================
+    StanzaPass("resolve-kinds"),
+    StanzaPass("infer-types"),
+    StanzaPass("check-types"),
+    StanzaPass("resolve-genders"),
+    StanzaPass("check-genders"),
+    StanzaPass("infer-widths"),
+    StanzaPass("width-check")
+// =====================================
     //ScalaPass(renamec)
+//  ScalaPass(renameall(Map(
+//    "c"->"ccc",
+//    "z"->"zzz",
+//    "top"->"its_a_top_module"
+//  ))),
+    // StanzaPass("temp-elim"), // performance pass
   ))
 
   // Parse input file and print to output
@@ -143,7 +149,7 @@ object Driver extends LazyLogging {
     logger.info(outfile)
 
     // finally, convert to verilog at the end
-    val cmd = Seq("firrtl-stanza", "-i", outfile, "-o", output, "-X", "verilog")
+    val cmd = Seq("firrtl-stanza", "-i", outfile, "-o", output, "-b", "verilog")
     logger.info(cmd.mkString(" "))
     val ret = cmd.!!
     logger.info(ret)
diff --git a/src/main/scala/firrtl/Passes.scala b/src/main/scala/firrtl/Passes.scala
index b73ee727..02016494 100644
--- a/src/main/scala/firrtl/Passes.scala
+++ b/src/main/scala/firrtl/Passes.scala
@@ -7,6 +7,9 @@ import Utils._
 import DebugUtils._
 import PrimOps._
 
+
+
+
 object Passes extends LazyLogging {
 
   // TODO Perhaps we should get rid of Logger since this map would be nice
@@ -42,8 +45,6 @@ object Passes extends LazyLogging {
    *    postponed for a later/earlier pass.
    */
   // input -> flip
-  private type TypeMap = Map[String, Type]
-  private val TypeMap = Map[String, Type]().withDefaultValue(UnknownType)
   private def getBundleSubtype(t: Type, name: String): Type = {
     t match {
       case b: BundleType => {
@@ -55,62 +56,52 @@ object Passes extends LazyLogging {
     }
   }
   private def getVectorSubtype(t: Type): Type = t.getType // Added for clarity
-  // TODO Add genders
-  private def inferExpTypes(typeMap: TypeMap)(exp: Expression): Expression = {
-    logger.debug(s"inferTypes called on ${exp.getClass.getSimpleName}")
-    exp.map(inferExpTypes(typeMap)) match {
-      case e: UIntValue => e
-      case e: SIntValue => e
-      case e: Ref => Ref(e.name, typeMap(e.name))
-      case e: SubField => SubField(e.exp, e.name, getBundleSubtype(e.exp.getType, e.name))
-      case e: SubIndex => SubIndex(e.exp, e.value, getVectorSubtype(e.exp.getType))
-      case e: SubAccess => SubAccess(e.exp, e.index, getVectorSubtype(e.exp.getType))
-      case e: DoPrim => lowerAndTypePrimOp(e)
-      case e: Expression => e
-    }
-  }
-  private def inferTypes(typeMap: TypeMap, stmt: Stmt): (Stmt, TypeMap) = {
-    logger.debug(s"inferTypes called on ${stmt.getClass.getSimpleName} ")
-    stmt.map(inferExpTypes(typeMap)) match {
-      case b: Begin => {
-        var tMap = typeMap
-        // TODO FIXME is map correctly called in sequential order
-        val body = b.stmts.map { s =>
-          val ret = inferTypes(tMap, s)
-          tMap = ret._2
-          ret._1
+  private type TypeMap = Map[String, Type]
+  /*def inferTypes(c: Circuit): Circuit = {
+    val moduleTypeMap = Map[String, Type]().withDefaultValue(UnknownType)
+    def inferTypes(m: Module): Module = {
+      val typeMap = Map[String, Type]().withDefaultValue(UnknownType)
+      def inferExpTypes(exp: Expression): Expression = {
+        //logger.debug(s"inferTypes called on ${exp.getClass.getSimpleName}")
+        exp.map(inferExpTypes) match {
+          case e: UIntValue => e
+          case e: SIntValue => e
+          case e: Ref => Ref(e.name, typeMap(e.name))
+          case e: SubField => SubField(e.exp, e.name, getBundleSubtype(e.exp.getType, e.name))
+          case e: SubIndex => SubIndex(e.exp, e.value, getVectorSubtype(e.exp.getType))
+          case e: SubAccess => SubAccess(e.exp, e.index, getVectorSubtype(e.exp.getType))
+          case e: DoPrim => lowerAndTypePrimOp(e)
+          case e: Expression => e
         }
-        (Begin(body), tMap)
       }
-      case s: DefWire => (s, typeMap ++ Map(s.name -> s.tpe))
-      case s: DefRegister => (s, typeMap ++ Map(s.name -> s.tpe))
-      case s: DefMemory => (s, typeMap ++ Map(s.name -> s.dataType))
-      case s: DefInstance => (s, typeMap ++ Map(s.name -> typeMap(s.module)))
-      case s: DefNode => (s, typeMap ++ Map(s.name -> s.value.getType))
-      case s: Conditionally => { // TODO Check: Assuming else block won't see when scope
-        val (conseq, cMap) = inferTypes(typeMap, s.conseq)
-        val (alt, aMap) = inferTypes(typeMap, s.alt)
-        (Conditionally(s.info, s.pred, conseq, alt), cMap ++ aMap)
+      def inferStmtTypes(stmt: Stmt): (Stmt) = {
+        //logger.debug(s"inferStmtTypes called on ${stmt.getClass.getSimpleName} ")
+        stmt match {
+          case s: DefWire => 
+             typeMap(s.name) = s.tpe
+             s
+          case s: DefRegister => 
+             typeMap(s.name) = get_tpe(s)
+             s
+          case s: DefMemory => 
+             typeMap(s.name) = get_tpe(s)
+             s
+          case s: DefInstance => (s, typeMap ++ Map(s.name -> typeMap(s.module)))
+          case s: DefNode => (s, typeMap ++ Map(s.name -> s.value.getType))
+          case s: s.map(inferStmtTypes)
+        }.map(inferExpTypes)
       }
-      case s: Stmt => (s, typeMap)
-    }
-  }
-  private def inferTypes(typeMap: TypeMap, m: Module): Module = {
-    logger.debug(s"inferTypes called on module ${m.name}")
+      //logger.debug(s"inferTypes called on module ${m.name}")
 
-    val pTypeMap = m.ports.map( p => p.name -> p.tpe ).toMap
-
-    Module(m.info, m.name, m.ports, inferTypes(typeMap ++ pTypeMap, m.stmt)._1)
-  }
-  def inferTypes(c: Circuit): Circuit = {
-    logger.debug(s"inferTypes called on circuit ${c.name}")
+      m.ports.for( p => typeMap(p.name) = p.tpe)
+      Module(m.info, m.name, m.ports, inferStmtTypes(m.stmt))
+    }
+    //logger.debug(s"inferTypes called on circuit ${c.name}")
 
     // initialize typeMap with each module of circuit mapped to their bundled IO (ports converted to fields)
     val typeMap = c.modules.map(m => m.name -> BundleType(m.ports.map(toField(_)))).toMap
-
-    //val typeMap = c.modules.flatMap(buildTypeMap).toMap
     Circuit(c.info, c.name, c.modules.map(inferTypes(typeMap, _)))
-  }
+  }*/
 
   def renameall(s : String)(implicit map : Map[String,String]) : String =
     map getOrElse (s, s)
diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza
index 6bce8ce4..0a07fcf0 100644
--- a/src/main/stanza/chirrtl.stanza
+++ b/src/main/stanza/chirrtl.stanza
@@ -5,6 +5,16 @@ defpackage firrtl/chirrtl :
    import firrtl/ir-utils
    import firrtl/primops
 
+
+; ===============================
+public val chirrtl-passes = to-list $ [
+   CInferTypes()
+   CInferMDir()
+   RemoveCHIRRTL()
+]
+; ===============================
+
+
 ; CHIRRTL Additional IR Nodes
 public definterface MPortDir
 public val MInfer = new MPortDir
@@ -55,7 +65,7 @@ defmethod map (f: Symbol -> Symbol, c:CDefMPort) -> CDefMPort :
 public defstruct CInferTypes <: Pass
 public defmethod pass (b:CInferTypes) -> (Circuit -> Circuit) : infer-types
 public defmethod name (b:CInferTypes) -> String : "CInfer Types"
-public defmethod short-name (b:CInferTypes) -> String : "c-infer-types"
+public defmethod short-name (b:CInferTypes) -> String : "cinfertypes"
 
 ;--------------- Utils -----------------
 
@@ -149,7 +159,7 @@ defn infer-types (c:Circuit) -> Circuit :
 public defstruct CInferMDir <: Pass
 public defmethod pass (b:CInferMDir) -> (Circuit -> Circuit) : infer-mdir
 public defmethod name (b:CInferMDir) -> String : "CInfer MDir"
-public defmethod short-name (b:CInferMDir) -> String : "cinfer-mdir"
+public defmethod short-name (b:CInferMDir) -> String : "cinfermdir"
 
 defn infer-mdir (c:Circuit) -> Circuit :
    defn infer-mdir (m:Module) -> Module :
@@ -209,7 +219,7 @@ defn infer-mdir (c:Circuit) -> Circuit :
 public defstruct RemoveCHIRRTL <: Pass
 public defmethod pass (b:RemoveCHIRRTL) -> (Circuit -> Circuit) : remove-chirrtl
 public defmethod name (b:RemoveCHIRRTL) -> String : "Remove CHIRRTL"
-public defmethod short-name (b:RemoveCHIRRTL) -> String : "remove-chirrtl"
+public defmethod short-name (b:RemoveCHIRRTL) -> String : "removechirrtl"
 
 defstruct MPort :
    name : Symbol
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 0d0191bf..e8c0acc8 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -176,8 +176,8 @@ public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> :
    ]
 
 ;============= DRIVER ======================================
-public defn run-backend (c:Circuit,comp:Compiler) :
-   run-passes(c,backend(comp))
+public defn run-backend (c:Circuit,pass:Pass) :
+   run-passes(c,list(pass))
 public defn run-passes (c:Circuit,comp:Compiler) -> Circuit: 
    run-passes(c,passes(comp))
 public defn run-passes (c:Circuit,ls:List<Pass>) -> Circuit:
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 2892cccc..39848088 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -32,6 +32,8 @@ defpackage firrtl-main :
    import stz/parser
    import firrtl/ir-utils
    import firrtl/compiler
+   import firrtl/chirrtl
+   import firrtl/firrtl
    ;Custom Packages
    ;import firrtl/custom-passes
    ;import firrtl/custom-compiler
@@ -48,7 +50,7 @@ defn set-printvars! (p:List<Char>) :
 
 defn get-passes (pass-names:List<String>) -> List<Pass> :
    for n in pass-names map :
-      val p = for p in standard-passes find :
+      val p = for p in append(standard-passes,chirrtl-passes) find :
          n == short-name(p)
       if p == false :
          error(to-string $ ["Unrecognized pass flag: " n])
@@ -134,8 +136,8 @@ defn main () :
    if compiler == false :
       var c*:Circuit = run-passes(circuit*,get-passes(to-list(pass-names)))
       switch {_ == backend} :
-        "verilog" : run-backend(c*,StandardVerilog(with-output))
-        "firrtl" : run-backend(c*,StandardFIRRTL(with-output))
+        "verilog" : run-backend(c*,LoToVerilog(with-output))
+        "firrtl" : run-backend(c*,FIRRTL(with-output))
         else : error("Invalid backend flag!")
    else :
       switch {_ == compiler} :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 503e16c4..7a94d59d 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -11,27 +11,25 @@ defpackage firrtl/passes :
 ;============== Pass List ================
 public val standard-passes = to-list $ [
    CheckHighForm()
-   ;TempElimination()
    ToWorkingIR()
    Resolve()
    ResolveKinds()
-   ;CheckKinds()
    InferTypes()
-   ;CheckTypes()
+   CheckTypes()
    ResolveGenders()
-   ;CheckGenders()
-   ;ExpandAccessors()
-   ;LowerToGround()
-   ;ExpandIndexedConnects()
-   ;InlineIndexed()
-   ExpandWhens()
+   CheckGenders()
    InferWidths()
-   ;Inline()
+   CheckWidths()
+   PullMuxes()
+   ExpandConnects()
+   RemoveAccesses()
+   ExpandWhens()
+   CheckInitialization()
+   ConstProp()
+   VerilogWrap()
    SplitExp()
-   ;CheckLowForm()
-   ;ToRealIR() 
-   ;Pad() 
-   ]
+   VerilogRename()
+]
 ;=============== WORKING IR ================================
 public definterface Kind
 public defstruct WireKind <: Kind 
@@ -1776,7 +1774,7 @@ defn resolve (c:Circuit) -> Circuit :
 public defstruct VerilogWrap <: Pass
 public defmethod pass (b:VerilogWrap) -> (Circuit -> Circuit) : v-wrap
 public defmethod name (b:VerilogWrap) -> String : "Verilog Wrap"
-public defmethod short-name (b:VerilogWrap) -> String : "v-wrap"
+public defmethod short-name (b:VerilogWrap) -> String : "verilog-wrap"
 
 public definterface WPrimOp <: PrimOp
 val ADDW-OP = new WPrimOp
@@ -2392,7 +2390,7 @@ defn lower-types (c:Circuit) -> Circuit :
 public defstruct VerilogRename <: Pass
 public defmethod pass (b:VerilogRename) -> (Circuit -> Circuit) : verilog-rename
 public defmethod name (b:VerilogRename) -> String : "Verilog Rename"
-public defmethod short-name (b:VerilogRename) -> String : "Verilog Rename"
+public defmethod short-name (b:VerilogRename) -> String : "verilog-rename"
 
 defn verilog-rename (c:Circuit) -> Circuit :
    defn verilog-rename-n (n:Symbol) -> Symbol :
@@ -2421,7 +2419,7 @@ public defstruct Verilog <: Pass :
    with-output: (() -> False) -> False  
 public defmethod pass (b:Verilog) -> (Circuit -> Circuit) : emit-verilog{with-output(b),_}
 public defmethod name (b:Verilog) -> String : "To Verilog"
-public defmethod short-name (b:Verilog) -> String : "To Verilog"
+public defmethod short-name (b:Verilog) -> String : "to-verilog"
 
 ;============ Utilz =============
 defstruct VIndent
@@ -2897,3 +2895,30 @@ defn emit-verilog (with-output:(() -> False) -> False, c:Circuit) :
    c
 
 
+;============ LoFIRRTLToVERILOG ==============
+
+public defstruct LoToVerilog <: Pass :
+   with-output: (() -> False) -> False  
+public defmethod pass (b:LoToVerilog) -> (Circuit -> Circuit) : lo-to-verilog{with-output(b),_}
+public defmethod name (b:LoToVerilog) -> String : "To LoToVerilog"
+public defmethod short-name (b:LoToVerilog) -> String : "lo-to-verilog"
+
+defn lo-to-verilog (with-output:(() -> False) -> False, c:Circuit) :
+   val c1 = to-working-ir(c)
+   ;println(c1)
+   val c2 = resolve(c1)
+   ;println(c2)
+   val c3 = v-wrap(c2)
+   ;println(c3)
+   val c4 = split-exp(c3)
+   ;println(c4)
+   val c5 = verilog-rename(c4)
+   ;println(c5)
+   emit-verilog(with-output,c5)
+
+
+
+
+
+
+